Copyright 2007 Society of Photo-Optical Instrumentation Engineers.
These papers were published in the SPIE Advanced Lithography proceedings and are made available as an electronic reprint (preprint) with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in these papers for a fee or for commercial purposes, or modification of the content of the papers is prohibited.
Patterning control budgets for 45-nm and 32-nm generations incorporating lithography, design and RET variations
Optical proximity correction in memory-device patterns using boundary layer model for 3D mask topography effect
Double patterning design split implementation and validation for the 32-nm node
Ensuring production-worthy OPC recipes using large test structure arrays
Intelligent visualization of lithography violations for 45-nm and beyond
Rapid search of the optimum placement of assist feature to improve the aerial image gradient in iso-line structure
Comparing traditional OPC to field-based OPC for 45-nm node production
Scanner-Characteristics-Aware OPC Modeling and Correction