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High Throughput GSPS Signal Processing for FPGAs and ASICs Using Synthesizable IP Cores

This whitepaper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or reduce power with sub-linear increases in area. The examples show how a vendor-independent, synthesizable IP approach can simultaneously achieve GSPS throughput and deliver excellent results across multiple hardware targets, while retaining an easy-to-use and productive design environment.

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