My RTL is an Alien!
FPGA-based prototyping is gaining popularity because it provides an economical way to functionally verify an ASIC design by creating a prototype that runs close to “at speed.” FPGA-based prototypes also provide a great platform for early system software development. However, FPGA architectures include resources, building blocks, power circuitry, and clocks that are fundamentally different from those of an ASIC. With over 70% of today's ASICs and systems-on-chips (SoCs) being prototyped in an FPGA, designers are looking for ways to ease the creation of FPGA-based prototypes directly from the ASIC design source files.
This paper focuses on how to create an automated process that converts ASIC design source files into a working FPGA. The techniques described will allow you to maintain one “golden” set of files that will work in both your ASIC and FPGA design environment so that, with each new revision of your ASIC design, you will be able to quickly create a revised FPGA-based prototype. This whitepaper complements the FPGA-Based Prototyping Methodology Manual, and several other documents that are available from Synopsys and listed at the end of this paper.
You will learn how to
- Create a reproducible scripted process for converting your ASIC design into a working FPGA-based prototype system. This is a way to batch automate the conversion process so that it can be re-run with each new ASIC “design drop.” It can be done using a combination of netlistediting functions, compiler constraints, 'define and ‘ifdef directives, and Tcl/Find scripting.
- Take ASIC design source files and add side files that render the design FPGA friendly to ensure that the design is synthesizable into the FPGA architecture and system. Topics covered will include reading the design in from the simulation verification environment, clock conversion, memory conversion, low power circuitry, and how to accommodate designs that contain ASIC IP.
- Obtain an initial working prototype as fast as possible.
- Meet design performance targets in the resulting FPGA-based prototype by tuning the initial prototype.