10 Ways to Effectively Debug your FPGA Design
Today's FPGAs implement the equivalent of millions of ASIC gates and continue to grow in size and complexity. When the design fails to synthesize or fails to operate as expected on the board, the designer is faced with the daunting task of determining the source of the failure from among potentially thousands of RTL and constraint source files, many of which have been authored by another designer. Given how lengthy design iteration runtimes have become, today's designs have an enormous need for better ways to find errors early and en masse. Smarter techniques to isolate errors and apply incremental fixes are also becoming a necessity.