Fast, Efficient RTL Debug for Programmable Logic Designs
Software simulation of RTL is no longer capable of providing all of the verification required for today‚Ä™s complex ASIC designs. (For the purposes of this paper, the term ASIC will be understood to encompass ASSP and SoC devices.) Modern ASICs are a complex mixture of hardware and software, and it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Thus, successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams.
As part of this, the ‚ÄúPrototyper‚ÄĚ specialist has emerged on the verification team. The Prototyper provides a unique knowledge mix of good verification practices, FPGA design savvy, and design-for-prototyping methodologies that help bring the benefits of the FPGA-based prototype to the design project. The Prototyper faces a daunting challenge with regard to creating a system that has satisfactory performance, is portable for field test, and is sufficiently inexpensive that multiple copies can be deployed to the hardware and software engineering teams concurrently.
During the ‚Äúbring-up phase‚ÄĚ of prototype design, multi-board systems are often required to provide physical interfaces and enough capacity to host the entire ASIC RTL. Creating a reliable hardware platform will inevitability require troubleshooting the circuit board connectors, cabling and partitioning logic. Following the bring-up phase, hardware debug can ensue. The ability to interface to real world stimulus and to achieve clock speeds fast enough to execute system software can dramatically increase test coverage. If something goes wrong, however, the Prototyper must employ some clever methods and tools to reveal logic defects buried within one or more FPGAs.
This paper examines some of the best practices for both successful bring-up and logic debug of FPGA-based ASIC prototypes.