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Synopsys hosts worldwide annual events for the PrimeTime Special Interest Group, providing an opportunity for PrimeTime users and design engineers to stay connected with the latest developments in the field of Static Timing Analysis (STA). We are pleased to host our 4th PrimeTime SIG event at SNUG India.
Featuring Next Generation Hierarchical Timing Technology - HyperScale Date: June13, 2012 - during SNUG India 2012
Time: 6:00 - 8:00pm
Location: ITC Gardenia, Bengaluru, Magnolia Ballroom
Address: No.1, Residency Road, Bengaluru , 560025, Karnataka, India Map
This year, the event will feature Synopsys' next generation hierarchical timing technology, HyperScale. Synopsys' R&D team will provide insight into the salient aspects of this technology and key customers will share their experience on qualifying and deploying it into their design flows, resulting in up to 10X faster and smaller full-chip timing analysis runs with the same signoff quality results compared to flat analysis.
To learn more about HyperScale, please read the EETimes article.
There will be a Question and Answer session at the end of the presentations for direct speaker-audience interaction. This event is open to Synopsys PrimeTime users and engineering managers. You are required to register for this event.
You can access the past SIG events online at the Synopsys website.
Agenda
Time
Topic
6:00 pm
Doors open
6:15 pm
Welcome and Introduction by Qualcomm Session Chair
6:20 pm
Presentations by LSI, NVIDIA, Texas Instruments and Synopsys
7:20 pm
Question and Answer session
7:30 pm
Prize drawing & Closing Remarks, buffet dinner to follow
* The dinner and beverages are complimentary.
Please complete the registration form:
We appreciate your answering the questions below. Thank you in advance.
1. Which PrimeTime release do you use for signoff timing and SI?
2010.06 or older
2010.12
2011.06
2011.12
Not using Primetime for timing signoff
2. For your current or most recent tapeout, please provide the following for your full-chip design:
b. Approximate PrimeTime SI runtime - design read through reporting (hours)
<2hr
2-4hr
5-8hr
9-16hr
>16hr
c. Approximate PrimeTime SI memory (GB)
<16GB
16-32GB
33-64GB
65-128GB
>128GB
3. Which of the following hierarchical STA models do you use in PrimeTime?
Interface Logic Model (ILM)
Extracted Timing Model (ETM)
Both
None, I do flat STA
4. What do you use for generating block level timing constraints/budgets?
Manual/spreadsheet mechanism
Internal scripts
Place and route tool
3rd party tool
Do Not Know
5. How often do timing constraints change during the timing closure phase?
Changes are frequent and made at top level
Changes are frequent and made at block level
Changes are rare and mostly made at top level
Changes are rare and mostly made within the block
6. What are the main reasons for constraint changes during final timing closure phase? (check all that apply)
Waiver mechanism for remaining violations
Incorporate DFT, logic simulation related changes
Adding or merging modes
Other, please specify:
7. If you run STA on hierarchical designs, how is full chip timing signoff run?
With flat constraints and flat parasitics
With flat constraints and hierarchical parasitics
With some blocks modeled as ILM's or ETM's
8. How do you perform timing ECOs for multiple instances of the same block in a design?
By uniquifying each instance in the layout and making instance-specific ECOs
By making ECO changes only at the top level while preserving multiple instances
By making ECO changes to a single instance with additional margin to cover other instances
No, do not have multi-instances at the top level
Other, please specify:
Please enter the verification code shown below: (What is this?)
