PrimeTime Special Interest Group (SIG) Luncheon Featuring Gigascale Design Signoff
Co-sponsored by GLOBALFOUNDRIES
Synopsys hosts worldwide annual events for the PrimeTime Special Interest Group, providing an opportunity for PrimeTime users and design engineers to stay connected with the latest developments in the field of Static Timing Analysis (STA). We are pleased to host our first event at DATE 2012, co-sponsored by GLOBALFOUNDRIES.
Date: 13, March 2012 - during DATE 2012
Time: 11:45 - 13:30
Location: ICC, Dresden - Hall 1
Address: Ostra-Ufer 2, 01067 Dresden, Germany 0351 2160 Map
The theme for this event is Gigascale Design Signoff with Advanced OCV, ECO Guidance and HyperScale technologies being showcased. Industry timing experts will share their experience on these new exciting technologies and Synopsys' Research and Development team will delve deeper into the underlying engines. There will be a Question and Answer session at the end of the presentations for direct speaker-audience interaction.
During the lunch event, attendees will have the opportunity to talk with industry peers and the PrimeTime Research and Development staff. This event is open to Synopsys PrimeTime users and engineering managers. To attend the PrimeTime SIG event at ICC, Dresden, you are required to register for both DATE 2012 Exhibition and PrimeTime SIG separately. Registration is free of charge. Synopsys does not provide DATE badges.
You can access the past SIG events online at the Synopsys website.
Introduction and Welcome by Synopsys Executive
Agenda and Speaker introduction by GLOBALFOUNDRIES Executive
Presentations by ARM, GLOBALFOUNDRIES, ST and Synopsys
Question and Answer session
Prize drawing & Closing remarks
* The luncheon is complimentary.
Please complete the registration form:
We appreciate your answering the questions below. Thank you in advance.
1. Do you plan to attend the DATE conference?
No ( Please register for the DATE 2012 Exhibition free of charge to attend the PrimeTime SIG luncheon)
2. Which of the following do you use to model variation effects? (check all that apply)
On-chip variation (OCV)
Advanced on-chip variation (AOCV)
Statistical STA (SSTA)
3. At what technology node did you start/plan to start using AOCV?
65nm or above
4. How many ECO iterations does it take for you to close a design?
More than 15
5. How many modes and corners do you fix in an ECO run?
# of Modes
10 or more
# of Corners
10 or more
6. Which of the following hierarchical static timing analysis (STA) models do you use?
Interface Logic Model (ILM)
Enhanced Timing Model (ETM)
None, I do flat STA
7. Are your block level constraints consistent with the top level to provide you predictable block level timing closure?
Do not know
8. If you run STA on hierarchical designs, do you close timing at all chip-level scenarios at the block before handing it off for chip-level analysis?
Yes, at all chip-level scenarios
No, only a subset
No, only one merged scenario
No, do not run STA on hierarchical designs
9. How would you like to be informed about PrimeTime updates and events? (check all that apply)
10. How would you like to get information about PrimeTime's latest technology? (check all that apply)