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Methods and Tools for Bring-Up and Debug of an FPGA-Based ASIC Prototype

Software simulation of RTL is no longer capable of providing all of the verification required for today's complex ASIC designs. Modern ASICs are a complex mixture of hardware and software, so it is necessary to verify the design within the context of the complete system, running the full range of software at speeds that approach real-time. Successfully validating an ASIC design on an FPGA-based prototype before committing to silicon is now a key project milestone for most design teams. This paper examines some of the best practices for both successful bring-up and logic debug of ASICs using FPGA-based prototypes.

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How is your current FPGA design being used? For prototyping an ASIC/SoC Being shipped in an end product

What is the primary challenge you face in FPGA design? Making my ASIC design FPGA-ready so that I can get my first prototype done quickly Debug and Analysis/Iteration Runtimes Mitigating Soft Errors Implementing Signal Processing Getting Timing closure and achieving target performance Creating Large Designs/Fast Turnaround Time Cost - Build vs. Buy Proof of concept

What is a secondary challenge you face in FPGA design? Making my ASIC design FPGA-ready so that I can get my first prototype done quickly Debug and Analysis/Iteration Runtimes Mitigating Soft Errors Implementing Signal Processing Getting Timing closure and achieving target performance Creating Large Designs/Fast Turnaround Time Cost - Build vs. Buy Proof of concept

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