TSMC 16nm-FinFET SRAM Design Verification
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The scaling of embedded SRAM into the 16nm technology node and beyond is critical for applications ranging from high-performance computing to low-power mobile devices. At 16nm, the emergence and use of FinFET 3D transistors bring many new opportunities to the SRAM design, but new challenges also accompany SRAM design verification. To address these challenges and enable efficient FinFET SRAM design, Synopsys and TSMC closely collaborated on enhancing the SPICE and FastSPICE tools for this node. Through FinFET BSIM-CMG model validation, IR/EM rules certification, SRAM instance pre-layout and post-layout, timing and power simulation calibration, and IR/EM simulation verification, the teams have established a working productive flow for 16nm-FinFET SRAM design verification.
Authors: Antony Fan, Mark Han, Amelia Shen, Weidong Liu, Vladimir Aptekar, Yen-Huei Chen, Wei-Min Chan, Hung-Jen Liao, Jonathan Chang, and Frank Lee