Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
In this issue, we have three independent perspectives on the economics of chip design. Dan Hutcheson, CEO of VLSI Research, thinks that the industry must retool its economic model for chip design and takes a fresh look at "design waste". According to Takashi Yoshimori, Assistant Technology Executive of SoC Design at Semiconductor Company of Toshiba Corporation, deeper collaboration and complete subsystems are critical to his organization's efforts to reduce design cost. And, Manoj Gandhi, Senior Vice President and General Manager, Synopsys' Verification Group, considers the leading role that verification occupies in design cost growth, and suggests new collaboration approaches for improving the economics of verification.
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