In this issue, we have three independent perspectives on the economics of chip design. Dan Hutcheson, CEO of VLSI Research, thinks that the industry must retool its economic model for chip design and takes a fresh look at "design waste". According to Takashi Yoshimori, Assistant Technology Executive of SoC Design at Semiconductor Company of Toshiba Corporation, deeper collaboration and complete subsystems are critical to his organization's efforts to reduce design cost. And, Manoj Gandhi, Senior Vice President and General Manager, Synopsys' Verification Group, considers the leading role that verification occupies in design cost growth, and suggests new collaboration approaches for improving the economics of verification.
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