Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
In this issue, we aim to de-mystify the art of analog design. Peter Frith, Wolfson Microelectronics' Chief Technology Officer, explains how his team manages the conflicting demands of analog transistors and digital gates within the same system. Dr. Paul Lo, Senior Vice President and General Manager of Synopsys' Analog/Mixed-signal Group, explains how standards will help shift the design of analog chips from an art to a managed discipline. And Joe Mastroianni, Synopsys' Vice President of Analog/Mixed-signal R&D, believes that tool developers must help designers to use their intuition.
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