Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Low power is the focus of this issue of Synopsys Journal. It is one of the biggest challenges that our customers face today. Its impact on the design flow is ubiquitous - from system specification through to process technology. Where will the next 100x power savings come from? Mike Muller, CTO, ARM Ltd., reviews low power market trends and concludes that however much the industry reduces power, it will never be enough. Dr. Antun Domic, Senior Vice President and General Manager of Synopsys Implementation Group, considers the business and technology issues that are driving change - both evolutionary and revolutionary - in low power design. And Michael Keating, Synopsys Fellow, reflects on key issues that affect the future of low power chip design.
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