Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
In this issue of Synopsys Journal, we consider the state-of-the-art in system-to-silicon verification. Paul Tobin, Director of the Verification Center of Expertise at AMD, discusses the evolution of AMD's processor development strategy, and highlights the importance of semiconductor IP to system-level verification. George Zafiropoulos, Vice President of Solutions Marketing at Synopsys, considers the results of a comprehensive survey of engineers, which help to shed light on some of the key issues facing system-to-silicon verification. And in a wide-ranging interview, Synopsys Journal's Rajiv Maheshwary, Senior Director of Solutions Marketing, asked Janick Bergeron, Synopsys Scientist and Fellow, about some of the key issues that verification teams face today, and the advanced verification techniques that can help them to verify across system boundaries.
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