Virtual Prototyping
Accelerate pre-RTL embedded software development, hardware/software integration, and system validation
Architecture Design
Quickly explore tradeoffs in your SoC architecture to achieve optimal product performance and cost to avoid over- or under-design
FPGA-Based Prototyping
Accelerate the creation of your ASIC prototype with a high-speed hardware prototyping environment including a comprehensive software flow
Core Optimization
Differentiate your product with the right combination of performance, power and area for your most design-critical cores
Design Flow Deployment
Optimize your design flow to address the latest design challenges
Physical Design Assistance
Leverage our tape-out proven flows and project experience to implement your very-deep submicron chip
IP Integration & SoC Verification
Get to market faster and reduce SoC design and verification cost by applying best practices in RTL creation and functional verification
Are your high-speed serial link simulations taking too long?
Want to speed up your eye diagram generation and ISI predictions by 100X?
If so, please join us for a free, informative technical webcast about how to speed up high-speed serial link analyses and get the most out of the new statistical eye diagram capability in HSPICE!
Overview Getting statistically-accurate predictions of inter-symbol interference (ISI) in high-throughput serial interfaces can require data stream simulations that are millions of bits long, and using traditional transient simulation approaches is very computationally expensive. A new approach is now available in HSPICE that uses fast statistical and convolution methods to directly generate eye diagram statistics. This new statistical eye diagram technique allows eye diagrams to be evaluated quickly and accurately. The result is convenient characterization of high-speed serial interfaces for fundamental statistical metrics including eye closure, bit error rate (BER), and bathtub curves.
Who should attend: IC and board-level analog design engineers and managers interested in signal integrity.
