Combining Formal Verification with Simulation: The Best of Both Worlds
Achieving complete verification of today's complex designs is, at best, a difficult and time consuming task that requires a combination of verification technologies. Design/verification teams use formal techniques to exhaustively prove functionality of small blocks, while resorting to simulation for full-chip verification. One of the barriers to using formal techniques has been the difficulty in leveraging an existing simulation environment. It has also been difficult to correlate the coverage information from formal tools with that from simulation. In this webinar, you will learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to remove these barriers.
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