Managing System Bandwidth With a High-Performance On-Chip Bus
Please join our webinar to learn how Synopsys' DesignWare® IP Solutions for AMBA® can help meet your performance goal, while reducing power, area and routing congestion.
In a typical system the bandwidth requirements for each interconnecting master and slave varies widely. Some master-slave links have high bandwidth requirements, while others have low latency requirements. Faced with growing demands on system performance, chip area and power, it becomes increasingly important to be able to effectively tune the interconnect fabric for each master-slave link in the system. This presentation details a flexible on-chip bus architecture that enables implementation of an interconnect fabric which delivers the highest of bandwidth for select links and reduced area, routing congestion and power for predefined lower performance links. The Hybrid architecture of the DesignWare Interconnect fabric for AMBA 3 AXI™ enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design.
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