In this three-day workshop, you will learn how use TetraMAX® to perform the following tasks:
- Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
- Describe the test protocol and test pattern timing using STIL
- Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
- Troubleshoot fault coverage problems
- Save and validate test patterns
- Troubleshoot simulation failures
- Diagnose failures on the ATE
This workshop also includes an overview of the fundamentals of manufacturing test, such as:
An overview of the Adaptive Scan and Power-Aware APTG features in TetraMAX® will also be presented.
- What is manufacturing test?
- Why perform manufacturing test?
- What is a stuck-at fault?
- What is a scan chain?
At the end of this workshop the student should be able to:
- Incorporate TetraMAX® ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
- Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, DFT Compiler, or from scratch
- Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
- Describe when and how to use at least three options to increase test coverage and/or decrease the number of required test patterns
- Save test patterns in a proper format for simulation and transfer to an ATE
- Validate test patterns in simulation using MAX Testbench
- Describe the difference between the Transition Delay and Path Delay fault models
- Use timing exceptions with At-Speed testing to mask slow cells
- Limit switching activity with Power-Aware ATPG
- Perform Transition Delay testing including Slack-Based Transition Delay
- Use On-Chip Clocking (OCC) to provide launch and capture clock pulse for At-Speed testing
- Generate critical paths from PrimeTime for performing Path Delay testing
- Use TetraMAX® diagnosis features to analyze failures on the ATE
ASIC, SoC, or Test Engineers who perform ATPG at the Chip or SoC level.
Prerequisites for the class include:
To benefit the most from the material presented in this workshop, students should have taken the DFT Compiler workshop or possess equivalent knowledge of DFT Compiler, scan insertion, and the fundamentals of manufacturing test.
- Understanding of digital IC logic design
- Working knowledge of Verilog or VHDL language
- Familiarity with UNIX workstations running X-windows
- Familiarity with vi, emacs, or other UNIX text editors
- Introduction to ATPG Test
- Building ATPG Models
- Running DRC
- Controlling ATPG
- Minimizing ATPG Patterns
- Pattern Validation
- Introduction to At-Speed Testing
- At-Speed Constraints
Synopsys Tools Used
- Transition Delay Testing
- On-Chip Clocking Support
- Path Delay Testing
- TetraMAX® 2013.12-SP3
- VCS 2014.03
- PrimeTime 2013.12-SP3