In this intensive, three-day course, you will learn the key features and benefits of the SystemVerilog testbench language and its use in VCS.
At the end of this class, students should have the skills required to write an object-oriented SystemVerilog testbench to verify a device under test with coverage-driven random stimulus using VCS.
First, students learn how to develop an interface between the SystemVerilog test program and the Device Under Test (DUT). Next, the workshop covers how the intuitive object-oriented technology in SystemVerilog testbench can simplify verification problems. This course concludes with an in-depth discussion of functional coverage including a uniform, measurable definition of functionality and the SystemVerilog constructs that allow you to assess the percentage of functionality covered either dynamically or through the use of generated reports.
To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
At the end of this workshop the student should be able to:
- Build a SystemVerilog verification environment
- Develop a stimulus generator to create constrained random test stimulus
- Develop device driver routines to drive DUT input with stimulus from generator
- Develop device monitor routines to sample DUT output
- Develop self-check routines to verify correctness of DUT output
- Abstract DUT stimulus as data objects
- Execute device drivers, monitors, and self-checking routines concurrently
- Communicate among concurrent routines using events, semaphores,and mailboxes
- Develop functional coverage to measure completeness of test
- Use SystemVerilog Packages
Design or Verification engineers who write SystemVerilog testbenches at the block or chip level.
To benefit the most from the material presented in this workshop,
students should have:
- A basic understanding of digital IC design
- Familiarity with UNIX workstations running X-windows
- Familiarity with vi, emacs, or other UNIX text editors
Synopsys Tools Used
- The Device Under Test
- SystemVerilog Verification Environment
- SystemVerilog Testbench Language Basics
- Driving and Sampling DUT Signals
- Managing Concurrency in SystemVerilog
- Object Oriented Programming: Encapsulation
- Object Oriented Programming: Randomization
- Object Oriented Programming: Inheritance
- Inter-Thread Communications
- Functional Coverage
- SystemVerilog VMM preview