Overview
Assertion based verification methodology has recently become a mainstream advanced verification methodology because of its myriad advantages. Assertions help capture the designer’s intent unambiguously and concisely thereby helping the designers to communicate the assumptions and specification in an executable format. Assertions also help Verification engineers to describe higher level protocol specifications in highly concise format and are highly reusable across designs, projects etc. SystemVerilog provides rich set of constructs for building assertions. It also enables creation of pre-defined checker libraries. Another benefit of assertions is that they can be used with dynamic and formal technologies.

This training is designed to introduce the Assertion Based Verification flow and the capabilities of the SystemVerilog assertions. Beginning with brief introduction to methodology, the course goes on to discuss various aspects of the SystemVerilog assertions with lot of examples. Debug with assertion is dealt with using the VCS’s DVE GUI. Other advanced topics like assertion coverage and mixed language assertion flow also would be dealt with. Hands-on lab session is given key priority to help concepts to be implemented as design examples.

Overall, course prepares you to smoothly integrate the SVA methodology without hardly any change to your current project environment.

• Write complex sequences and properties using SVA
• Start using the built-in checker assertions
• Use VCS based assertion flow and DVE debug for faster analysis
• Implement coverage assertion points
• Implement SVA in a mixed design flow

Audience Profile
Design / Verification Engineers

Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:

• Familiarity with design/verification flows.
• Knowledge in Verilog

• Introduction to assertions
• SVA checker library
• Use Model and debug flow using DVE
• Basic SVA constructs
• Temporal behavior, Data Consistency
• Coverage, Coding Guidelines

• VCS 2006.06