In this intensive, one-day course, you will learn the key features and benefits of the SystemVerilog Assertion language and its use in VCS.
This course is a hands-on workshop that reinforces the verification concepts taught in lecture through a series of labs. At the end of this class, students should have the skills required to write SystemVerilog Assertions to verify a device under test using VCS. Students will also learn how to use assertion libraries and obtain coverage information on assertions.
Students will first learn how to write immediate and concurrent assertions. Next the workshop will explain in depth the use of sequences to write assertions and make them reusable and scalable. The course then discusses assertion coverage and use of cover properties that allows you to assess the effectiveness and efficacy of your testbench. Lastly the course introduces you to the concept of assertion libraries to capture standard behaviors in a scalable, reusable form.
To reinforce the lecture and accelerate mastery of the material, each student will complete a challenging test suite for real-world, system-based design.
At the end of this workshop the student should be able to:
- Create immediate and concurrent assertions
- Use reusable properties and sequences in assertions
- Embed assertions in the testbench
- Develop separate modules for assertions and bind them to the components of the testbench
- Debug assertion output using DVE
- Use cover properties
- Use assertion libraries
- Measure coverage on assertions and cover properties
Design or Verification engineers who write SystemVerilog testbenches at the block or chip level
To benefit the most from the material presented in this workshop, students should have:
- An understanding of basic concepts of design verification
- Working knowledge of SystemVerilog. Students should preferably have completed the SystemVerilog Testbench course offered by Synopsys
- Experience with a high-level programming language (such as C)
- Familiarity with UNIX workstations running X-windows
- Familiarity with vi, emacs or other UNIX text editor
- Immediate and Concurrent Assertions
- Assertion Coverage
- Assertion Libraries
Synopsys Tools Used
- VCS 2014.12
- Verdi3 2014.12-1