Overview
The workshop is based on Synopsys’ Lynx Compatible Reference Methodology (LCRM) flow:

• The “MCMM Data Setup” unit covers how to load the files and libraries required by IC Compiler, as well as setting up scenarios for multi-corner multi-mode (MCMM) analysis and optimization.
• The “Design Planning” unit covers how to create a block-level floorplan, including macro placement and a power network, which results in acceptable routeability and timing throughout the flow.
• The “Placement” unit focuses on optimizing the placement and logic for timing, congestion, leakage power, and scan-chain ordering.
• The “Clock Tree Synthesis” (CTS) unit covers controlling and building clock trees, optimizing clock power dissipation, and performing additional timing optimization.
• The “Routing” unit covers routing of the clock nets, followed by signal routing and optimization, including redundant via insertion, antenna fixing, and crosstalk reduction.
• The “Design for Manufacturability” unit covers steps to improve yield and reliability, including wire spreading/widening, diode insertion, inserting filler cells, redundant via insertion, and signoff metal filling using IC Validator. The unit concludes by covering how to generate design data for final verification and validation, as well as converting the block into a hard macro for top-level integration.

Every lecture is accompanied by a comprehensive hands-on lab. Labs use the LCRM directory structure and scripts.

• Use the GUI to analyze the layout during the various design phases
• Perform and debug data setup to create an initial design cell which is ready for design planning and placement; This includes loading required files and libraries, creating a Milkyway design library, and applying common timing and optimization controls
• Create scenarios for MCMM timing, leakage power, and CTS optimization
• Create a non-hierarchical block-level floorplan for always-on single-voltage (non-UPF) designs that will be routable and will achieve timing closure
• Perform standard cell placement and related optimizations to minimize timing violations, congestion, and leakage power; Insert spare cells
• Analyze congestion maps and timing reports
• Apply any required CTS constraints, targets, and controls
• Perform pre-CTS power optimization to reduce clock tree power
• Execute the recommend clock tree synthesis and optimization flow
• Analyze clock tree and timing results post-CTS
• Perform routing setup to control DRC fixing, delay calculation, redundant via insertion, antenna fixing, and crosstalk reduction
• Route the clock nets
• Route the signal nets and perform post-route optimization
• Analyze and fix physical DRC and LVS violations
• Perform functional ECOs
• Perform design for manufacturability steps
• Generate output files required for final validation/verification

Audience Profile
ASIC, back-end, or layout designers who will be using IC Compiler to implement a complete flat, non-UPF, block-level physical design flow.

Prerequisites
Prior knowledge of IC Compiler is not needed. An understanding of basic physical design, layout or standard cell place & route concepts and terms is helpful, including: Standard cells and libraries; Floorplanning, placement and routing fundamentals; Causes and effects of congestion; Setup and hold timing, and clock skew.

Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.

• Introduction
• MCMM Data Setup
• Design Planning

• Design Planning (Lab continued)
• Placement
• Clock Tree Synthesis

• Clock Tree Synthesis (Lab continued)
• Routing
• Design for Manufacturability
• Customer Support

• IC Compiler - Version 2012.06-SP3
• IC Validator – Version 2012.06-SP1
• Lynx – Version 2012.06-SP2