IC Compiler 1

In this hands-on workshop, you will be using IC Compiler to implement a block-level physical design flow on a “flat” (non-hierarchial) design. This includes performing placement, clock tree synthesis, routing, and design for manufacturability, with a focus on routability, while meeting timing and reducing power.

Day 1 covers “data setup” for concurrent “multi-corner multi-mode” (MCMM) optimization, including “on-chip variation” (OCV) effects, followed by an overview of basic floorplanning steps (non-hierarchical) of a non-UPF, block-level design, and congestion analysis.

Day 2 covers standard cell placement and logic optimation which includes: Control setup, placement with recommended optimizations, and incremental post-placement optimation techniques; The clock tree synthesis unit covers: Control setup, clock-gating optimization, CTS, post-CTS optimizations and clock tree analysis.

Day 3 covers routing: Control setup, clock and signal routing, post-route optimization, DRC fixing, and functional ECOs; The workshop concludes with “Design for Manufacturability” techniques for improving yield and reliability, and design data generation for final verification and validation.

The workshop is based on Synopsys’ “Lynx Compatible Reference Methodology” (LCRM) flow. Every lecture is accompanied by a comprehensive hands-on lab. Labs use the LCRM directory structure and scripts.

At the end of this workshop you should be able to use IC Compiler to:
  • Use the GUI to analyze the layout during the various design phases
  • Perform and debug data setup to create an initial design cell which is ready for design planning and placement; This includes loading required files and libraries, creating a Milkyway design library, and applying common timing and optimization controls
  • Create scenarios for concurrent MCMM optimization during placement, CTS and routing
  • Account for on-chip variation during timing analysis and optimization
  • Apply timing and optimization controls which apply to the entire P&R flow
  • Create a basic floorplan (non-hierarchical, non-UPF, block-level: Define core shape, pin placement and macro placement; Define placement blockages; Execute a script which invokes TPNS to build the power network structure
  • Perform pre-placement control setup and checks
  • Perform setup for integrated clock-gating (ICG) cell optimization
  • Perform concurrent MCMM standard cell placement and related optimizations to minimize timing violations, congestion, and power; Includes magnet placement, inserting spare cells, and creating move bounds
  • Perform incremental post-placement optimzations to improve congestion and timing
  • Analyze congestion maps and timing reports
  • Apply re-CTS setup steps to define CTS scenarios, constraints/targets, controls and NDR rules
  • Invoke pre-CTS power optimization to reduce clock tree power
  • Execute the recommend clock tree synthesis and optimization flow to build a skew-balanced clock tree network
  • Perform post-CTS logic optimization, including hold time fixing
  • Invoke incremental CTS and logic optimization techniques as needed
  • Analyze clock tree and timing results post-CTS
  • Perform routing setup to control DRC fixing, delay calculation, via optimization, antenna fixing, and crosstalk reduction
  • Route the clock nets
  • Route the signal nets and perform post-route optimization
  • Analyze and fix physical DRC violations, using IC Validator from within IC Compiler
  • Perform functional ECOs
  • Execute design for manufacturability steps to improve yield and reliability, including diode insertion, filler cell insertion, incremental via optimization, and signoff metal filling using IC Validator
  • Generate output files required for final validation/verification
  • Convert the completed block-level design into a soft macro

Audience Profile
ASIC, back-end, or layout designers who will be using IC Compiler to perform physical design on a block-level design

Prior knowledge of IC Compiler is not needed.

An understanding of basic physical design, layout or standard cell place & route concepts and terms is helpful, including: Standard cells and libraries; Floorplanning, placement and routing fundamentals; Causes and effects of congestion; Setup and hold timing, and clock skew.

Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.

Course Outline
Day 1
  • Introduction (Lecture + Lab)
  • MCMM Data Setup (Lecture + Lab)
  • Design Planning (Lecture)
Day 2
  • Design Planning (Lab)
  • Placement (Lecture + Lab)
  • Clock Tree Synthesis (Lecture)
Day 3
  • Clock Tree Synthesis (Lab)
  • Routing (Lecture + Lab)
  • Design for Manufacturability (Lecture + Optional Lab)
  • Customer Support (Lecture)

Synopsys Tools Used
  • IC Compiler - Version 2013.03-SP2
  • IC Validator – Version 2013.06-SP1
  • Lynx – Version 2013.03-SP2