Overview
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT checks and to insert scan using top-down and bottom-up flows. The workshop will show you how to analyze the reported data to identify common DFT violations and then fix the original RTL design.

The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing; inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

• Create a test protocol for a design and customize the initialization sequence, if needed, to prepare for DFT DRC checks
• Perform DFT DRC checks at the RTL, pre-DFT, and post-DFT stages
• Recognize common design constructs that cause typical DFT violations
• Automatically correct certain DFT violations at the gate level using AutoFix
• Implement top-down scan insertion flow achieving well-balanced scan chains
• Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route
• Develop a bottom-up scan insertion script for full gate-level designs to use Test Models at the top-level to improve capacity and runtime
• Insert an On-Chip Clocking (OCC) controller to use for At-Speed testing with internal clocks
• Modify a scan insertion script to include DFTMAX Adaptive Scan compression

Audience Profile
Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million gate SoCs, and export design files to ATPG and P&R tools

Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision and writing Synopsys Tcl scripts is useful, but not required.

• Introduction to Scan Testing
• DFT Compiler Flows
• DFT Compiler Setup
• Test Protocol
• DFT Design Rule Checks

• DFT DRC GUI Debug
• DRC Fixing
• Top-Down Scan Insertion
• Exporting Files

• High Capacity DFT Flows
• On-Chip Clocking (OCC)
• Multi-Mode DFT
• DFTMAX

• DFT Compiler 2011.09-SP4
• Design Vision 2011.09-SP4
• Design Compiler 2011.09-SP4
• TetraMAX 2011.09-SP4