HOME    SUPPORT    TRAINING COURSES

Training

DFT Compiler

Overview
In this workshop you will learn to use DFT Compiler to perform RTL and gate-level DFT rule checks, fix DFT DRC rule violations, and to insert scan using top-down and bottom-up flows. The workshop explores essential techniques to support large, multi-million gate SOC designs including the bottom-up scan insertion flow in the logical (Design Compiler) domain. Techniques learned include: performing scan insertion in a top-down flow; meeting scan requirements for number of scan chains, maximum chain length and reusing functional pins for scan testing, inserting an On-Chip Clocking (OCC) controller for At-Speed testing using internal clocks; and using Adaptive Scan (DFTMAX) to insert additional DFT hardware to reduce the test time and the test data volume required for a given fault coverage.

Objectives
At the end of this workshop the student should be able to:
  • Create a test protocol for a design and customize the initialization sequence, if needed, to prepare for DFT DRC checks
  • Perform DFT DRC checks at the RTL, pre-DFT, and post-DFT stages
  • Recognize common design constructs that cause typical DFT violations
  • Automatically correct certain DFT violations at the gate level using AutoFix
  • Implement top-down scan insertion flow achieving well-balanced scan chains
  • Write a script to perform all the steps in the DFT flow, including exporting all the required files for ATPG and Place & Route
  • Develop a bottom-up scan insertion script for full gate-level designs to use Test Models at the top-level to improve capacity and runtime
  • Insert an On-Chip Clocking (OCC) controller to use for At-Speed testing with internal clocks
  • Modify a scan insertion script to include DFT-MAX Adaptive Scan compression

Audience Profile
Design and Test engineers who need to identify and fix DFT violations in their RTL or gate-level designs, insert scan into multi-million gate SoCs, and export design files to ATPG and P&R tools

Prerequisites
There are no prerequisites for this workshop. Prior experience with Design Compiler, Design Vision and writing Synopsys Tcl scripts is useful, but not required.

Course Outline
Day 1
  • Introduction to Scan Testing
  • DFT Compiler Flows and Setup
  • Test Protocol
  • DFT Design Rule Checks

Day 2
  • DFT DRC GUI Debug
  • DRC Fixing
  • Top-Down Scan Insertion
  • Exporting Files

Day 3
  • High Capacity DFT Flows
  • On-Chip Clocking (OCC)
  • Multi-Mode DFT
  • DFT MAX

Synopsys Tools Used
  • DFT Compiler 2013.12-SP3
  • Design Vision 2013.12-SP3
  • Design Compiler 2013.12-SP3
  • TetraMAX 2013.12-SP3