Overview
This course covers implementation of Self Test and Repair (STAR) Memory System in the ASIC flow. You will learn how to read configure and generate components of STAR memory System; Implement and Verify STAR memory system in your design; Generate necessary constraints for synthesize and timing verification; Implement Test and Repair flow of Embedded Memory IP on ATE; Implement diagnostic and debug flow for Embedded memory IP.

Objectives

At the end of this workshop the student should be able to:

• Perform a high level project planning for test and repair of embedded memories
• Generate STAR memory system (SMS) components according to the project configuration
• Insert SMS components into the design hierarchy
• Generate constraints required for design implementation flow
• Implement test and repair flow for embedded memory IP at the design top level
• Verify SMS in the design environment
• Generate and verify ATE patterns for memory test and repair using e-fuses
• Generate and verify ATE pattern for memory defect bit mapping
• Generate verify pattern for memory debug using programmable test algorithm

Audience Profile
The class attendees will be SoC design and/or DFT engineers.

Prerequisites
To benefit the most from the material presented in this workshop, students should:

• Understand the functionality of digital sequential and combinational logic.
• Be familiar with Verilog language.
• Understand Chip test and through JTAG interface.

• Introduction to STAR Memory System
• Memory architecture
• Overview of Integrator and generating memories
• Generating Memories (only Synopsys memory customers)
• SMS overview and Project planning
• SMS Components
• Verification of generated SMS
• Insertion of SMS into design Sub Chip (block) level
• Verification of SMS at SubChip (block) level
• SMS Server
• Verification of SMS Server
• Labs 1-8

• SMS Integration into design Chip (design top) Level
• SMS Verification at Chip (design top) level
• Generating manufacturing test and repair flow
• Collecting failure bitmap (silicon debug)
• Programmable test algorithm
• Labs 9-13

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