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Asic Prototyping with the Certify™  Tool 

Overview
This course introduces concepts on ASIC prototyping using the Certify ASIC Prototyping tool. Designers can take this course at their own pace and enjoy the online version of this class. Comprehensive notes complete the information displayed on each page. This course is powered by Vitalect.

Objectives
The focus will be on understanding concepts on RTL-level partitioning, and using the Certify product to create a successfully partitioned design. Students will learn:
  • Certify Product Concepts
  • Understanding the Certify UI
  • Specification of Prototype Board Descriptions
  • Partitioning to FPGA Devices

Audience Profile
Designers who wish to create successful FPGA-based prototypes of their ASIC designs utilizing the Certify product.

Prerequisites
Familiarity with prototyping issues and experience in Verilog or VHDL design and logic synthesis.

Course Outline
  • Project Management
  • RTL Prototyping Concepts
  • Defining a Board Description File
  • Quick Partitioning Technology
  • Advanced Partitioning Tools
  • Area Estimation
  • Creating a Successful Partition
  • Hierarchical Systems
  • Debug Insertion Features
  • Performing Pin Assignment
  • MultiPoint™ Synthesis Flow

Synopsys Tools Used
  • Certify

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