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SNUG Taiwan 2009 Proceedings

Complete Proceedings

User Papers and Presentations
Partner User Presentation
TSMC N28/N32/N40 Test Chip Design Flow with Synopsys
Author(s): Charles Liu [TSMC]
Presentation

TD1 - UPF Low Power
Hierarchical Low Power Design Flow
Author(s): Hsiao Cheng Wang [TSMC]
Presentation

UPF-Compliant Library/Environment in the Multi-Supply Multi-Voltage Era (Best Paper Award)
Author(s): Steve Tsai [Faraday Technology]
Paper Presentation

TD2 - VMM-LP/VMM Aplication/PVCS
Expedite Multi-Core Simulation with Parallel VCS
Author(s): James Lai [Andes Technology]
Presentation

Hook Up VMM RAL To DUT Within 10 Minutes
Author(s): Shang-Wei Tu, Yi-Hsiang Chou, Tom Lin [Sunplus]
Paper Presentation

TD3 - Fast SPICE
Accelerates Pre/Post Layout Flash Memory Simulation in HSIM flow
Author(s): Perry Huang [Macronix]
Paper Presentation

TSMC Power Rail Reliability Methodology by HSIMplus PWRA and SBA
Author(s): M.J. Huang [TSMC]
Presentation

TE2 - Low Power Verification/VMM
UPF Low Power Verfication Experience Sharing
Author(s): Chen-An Chen [Industrial Technology Research Institute]
Presentation

TE3 - Custom Design
Dance with Nanotime
Author(s): Jack Liu [TSMC]
Presentation

TSMC iPDK
Author(s): Steven Chen [TSMC]
Presentation

WA1 - Physical Design
Achieving best timing and runtime results by using IC Compiler ZRoute
Author(s): Ryan Su [Realtek]
Paper Presentation

Maximize Power Saving by Timing-Driven Clock Gating in Galaxy Platform (Best Paper Award)
Author(s): Jeff Hsieh [Sunplus]
Presentation

WA2 - Advanced Test
Boundary Scan Insertion for Multi-Voltage Island Design
Author(s): C.T.Kao [Faraday Technology]
Presentation

High Speed Design DFT Practice
Author(s): Karl Chang [Global Unichip Corporation]
Presentation

WA3 - Synplicity
Multi-FPGA prototyping for SOC function verification
Author(s): Chao-Yang Chen [ ALi Corporation]
Presentation

Rapid prototyping of WiMax chip uses HAPS34/HAPS54
Author(s): Jeff, Teng-Chieh Yang [Industrial Technology Research Institute]
Presentation

The Best FPGA Timing Closure and Debugging Solution
Author(s): Pearson [Faraday Technology]
Presentation

WB1 - Physical Design
Achieve GHz+ CPU by Using IC Compiler in Cell-Based ASIC Design
Author(s): [Faraday Technology]
Presentation

Methodology Share for Die Driven Flow of Flip Chip in IC Compiler (Best Paper Award)
Author(s): S.C. Tsai [Progate Group Corporation]
Paper Presentation

WB2 - Synthesis/STA/EC
Design Compiler Graphical: A New Congestion Prediction and Reduction Flow starting from RTL
Author(s): Eric Wang [Realtek]
Paper Presentation

Equivalency check with Formality - Perspectives of Completeness and Productivity
Author(s): [Progate Group Corporation]
Presentation

Publication Only
For Publication Only
Performance Evaluation of Multilayer AHB Bus Matrix For High Bit-Rate, Mesh Applications
Author(s): Suhaimi Bahisham Jusoh @ Yusoff, Wan Suzila, Wan Husain, Nor Azura Zakaria [Mimos Berhad]
Paper

Tutorials
TD1
Design Compiler and IC Compiler 2008.09 Multi-Voltage IEEE P1801 (UPF) Methodology Update
Author(s):
Tutorial

TD2
VMM-Low Power
Author(s):
Tutorial

TD3
Utilizing and Understanding HSIM for Accuracy and Performance Tuning
Author(s):
Tutorial

TE1
PrimeRail and ICC: In-Design Rail Analysis for Faster Physical Power Network Design Closure
Author(s):
Tutorial

Improving RTL-to-GDSII Design Efficiency
Author(s):
Tutorial

TE2
Efficient Constraint Solving and Debugging with VCS
Author(s):
Tutorial

Multi Voltage Verification for High End Mobile Processor Design
Author(s):
Tutorial

TE3
Synopsysí Custom Design Solution
Author(s):
Tutorial

WA1
Zroute: New, DFM-Friendly and Multi-Threaded Routing Technology in IC Compiler
Author(s):
Tutorial

WA2
Galaxy Test:Power-Aware DFT/ATPG and Technical Updates
Author(s):
Tutorial

WB1
ICV and ICC: signoff DRC and metal fill
Author(s):
Tutorial

WB2
Design Compiler: Accelerating Design Closure
Author(s):
Tutorial

Faster Timing Closure in a Multi-Scenario World
Author(s):
Tutorial

WB3
USB 3.0 Controller - How to Address System-Level Issues in your USB 3.0 Designs
Author(s):
Tutorial

DDRn - Constructing Timing Budgets and Improving Timing Margins for DDRn Memory Interfaces
Author(s):
Tutorial