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Synopsys Users Group

SNUG Taiwan 2008 Proceedings

User Papers and Presentations
AMS
An Automatic Analog Design Optimization Platform
Author(s): Wells Jong, David Wu, Joseph Chang [Faraday]
Paper Presentation

Flash Memory Function Simulation using HSIM Flash Cell Model
Author(s): Shin-Jang Shen [Macronix]
Paper Presentation

DFY, IP, & Prototyping
Experience Sharing of Synopsys ASIC Prototyping Flow with HAPS
Author(s): Jeff, Teng-Chieh Yang [Industrial Technology Research Institute]
Presentation

TSMC DFM Ecosystem
Author(s): Yi-Kan Cheng [TSMC]
Presentation

Low Power
Power Gating Implementation Techniques for 90nm IP Library
Author(s): Li Ju Chi [NOVATEK MIicroelectronics]
Paper Presentation

The Enabling Technologies for High-Performance Low Power CPU Design
Author(s): Sean Fan, Ean Tseng, J.D. Pan, Grace Sun [Faraday]
Paper Presentation

UMC-Synopsys 65nm Low Power UPF Reference Flow
Author(s): Kevin Liu [UMC], Wendy Chen [Synopsys]
Paper Presentation

Voltage Assignment and Partition for Multi-Voltage Island Design
Author(s): C.T.Kao [Faraday]
Paper Presentation

Physical Design
An Implementation Methodology Based on ICC Whole Flow
Author(s): ChangYuan-Cheng, Kim-Liu, Minno-Hsiao [Sunplus Technology]
Presentation

Astro and ICC CTS structure handling for clock gating structure
Author(s): Herbert Shen [Realtek Semiconductor Corp.]
Paper Presentation

IC Complier Application to VIA's Project Implementation
Author(s): Babbit Wang [VIA Inc.]
Presentation

Synthesis, STA, and Test
Building Cost Effective Systems with AndesCore Processors
Author(s): James Lai [Andes Technology]
Presentation

Experiences in DFT MAX Scan Compression Flow
Author(s): Jih-Nung Lee, Shuo-Fen Kuo, Chih-Hung Wu, Chi-Feng Wu, and Shih-Arn Hwang [Realtek Semiconductor Corp.]
Paper Presentation

Verification
A case study of VMM adoption
Author(s): YS Chou [Sunplus Technology]
Paper Presentation

Formal is easy WiMax Application with Magellan
Author(s): Chan-Chi Wu [Industrial Technology Research Institute]
Presentation

Migrations from VERA to VMM
Author(s): Cheng Chung-Yuan [Realtek Semiconductor Inc.]
Paper Presentation

Tutorials
Tutorials
45/40nm circuit simulation challenge
Author(s):
Tutorial

Addressing New IP Challenges in SoC Designs
Author(s):
Tutorial

Circuit Verification Technology with HSIM for Deep Nanometer Design
Author(s):
Tutorial

Congestion Prediction and Reduction Using Design Compiler Graphical
Author(s):
Tutorial

Getting the Best Performance From PrimeTime
Author(s):
Tutorial

Getting to Market Early with Pre-Silicon Software Development on Virtual Platforms
Author(s):
Tutorial

Identification and Correction of Design Hotspots using Synopsys PrimeYield and IC Compiler
Author(s):
Tutorial

SuccessConcurrent Hierarchical Design Planning and Implementation Using Galaxy 2007.12
Author(s):
Tutorial

SuccessIC Compiler RM : Reference Methodology with emphasis on Concurrent MCMM & Signoff Driven Design Closure
Author(s):
Tutorial

Synopsys UPF Low Power Implementation Flow & ARM1176JZF-S Implementation
Author(s):
Tutorial

The Pilot Design Environment:A production design flow for 65nm Low Power Designs
Author(s):
Tutorial

Voltage Drop Sign-Off withIC Compiler and PrimeRail
Author(s):
Tutorial

Guest Presentation
Guest Presentation
Low Power Multi-voltage Verification on APX 2500
Author(s):
Presentation

Replacing an In-Circuit Emulation Environment with a SystemVerilog Transaction-Level TestBench
Author(s):
Presentation