Synopsys Users Group

SNUG Taiwan 2005 Proceedings

User Papers and Presentations
User Papers
A Fast Methodology Flow for IP Input and Max Output Cap Characterization
Author(s): Peter H Chen, Harrison Liu, Peter Pong, Jim Wang, and Jerry Hong [Faraday Technology Corporation]
Paper Presentation

A Systematic Approach to Trace Netlist for ECO
Author(s): Ling-Bin Guo [Infineon-ADMtek]
Paper Presentation

An Efficient RTL to GDSII Implementation Platform Based on Galaxy Design Environment
Author(s): Jeff Hsieh [Sunplus Technolog Co, Ltd]

Chip Level Planning Using JupiterXT
Author(s): Hung-Yi Kuo and Jago Huang [ALI]

Dissect Location-Based On Chip Variation
Author(s): Jerry Hong, Erica Chang and JD Pan [Faraday Technology Corporation]
Paper Presentation

Experience of Lower Power Design Methodology with Dynamic Frequency and Voltage Scaling in SoC Design
Author(s): Dave Scott and Sachin Idgunji [Synopsys], Dar-Sun Tsien [UMC], Dave Flynn [ARM], Lumdo Chen [UMC]

Improving Verification Productivity with VCS Native Testbench
Author(s): Kuei-Ju Yang and CY Cheng [Realtek Semiconductor Corp]

Leakage Power Optimizatoin for 0.13um Process Design
Author(s): Wei-Liang Ying [Sunplus]

Memory Model Verification in ESP-CV
Author(s): Jia-Liang Chiou and Jian-Dai Pan [Faraday Technology Corporation]
Paper Presentation

Noise Library for PrimeTime-SI
Author(s): Peter Chih-Yang Pong and Steve H. Tsai [Faraday Technology Corporation]
Paper Presentation

SI Solution Using Astro-Xtalk
Author(s): Jerming Lin [VIA Technologies]

Sub-100nm Technology Development and Optimization: Integration of TCAD with Yield Management
Author(s): T. Akiyama, H. Yoshimura and S. Komatsu [Toshiba Corporation], L. Bomholt, G. Braun, C. Zechner, S. Krishnamurthy, H. Takada and W. Fichtner [Synopsys Inc], K. Zafar and E. Chang, [KLA-Tencor Inc]
Paper Presentation

Timing Closure & Signoff Flow
Author(s): Wen Hung Wu [ALi Corporation]

Verification: Moving Toward the Next Generation
Author(s): Chung-HsingChen [VIA Technologies Inc]