Synopsys Users Group

SNUG Singapore 2008 Proceedings

User Papers and Presentations
User Sessions
Achieving Good Clock Skew and Inter-Clock Balancing Results Using ICC CTS Flow (1st Place - Best Paper)
Author(s): Teng, Siong Kiong, Lim, Mui Liang [Intel Corporation]
Paper Presentation

ARM-based SoC Verification with SystemVerilog Functional Coverage (2nd Place - Best Paper)
Author(s): Thia Chin Tong, Cheow Wai Meng, Tan Lay Hong [Solomon Systech Pte. Ltd.]
Paper Presentation

Cost Effective Metal-mask ECO Flow (3rd Place - Best Paper)
Author(s): Sudhakar Sayana [Infineon Technologies]
Paper Presentation

Cross Voltage PV Convergence using Empirical Analysis
Author(s): Wan Chong Khor, Aan Chien Tan, Kok TiongTee [Intel Corporation]
Paper Presentation

Multi-Clock Domain TDF ATPG Testing: An Innovative Approach
Author(s): Chin Hai Ang [Altera Corporation]
Paper Presentation

Noise Modeling In 45nm Designs
Author(s): Ang Boon Chong, Teoh Chea Ying [Altera Corporation]
Paper Presentation

Structured ASIC Macro Cell Timing Model Characterization using NanoTime
Author(s): Ang Shor Lin Lim,Teik Wah, Lim, Yun Mei [Altera Corporation]
Paper Presentation

System-C and RTL Co-Simulation Environment with Power Management Model
Author(s): Thai Minh Nguyen [Renesas Design]
Paper Presentation

Publication Only
For Publication Only
An Automated Flow to Detect Critical Manufacturing Hotspots using SiVL
Author(s): Sik Shu Teng, Sidney Ng [Systems on Silicon Manufacturing Co.]

CCS vs NLDM In 45nm Designs
Author(s): Ang Boon Chong, Sherine Ang Shor Lin [Altera Corporation]

How to Handle OCC (On Chip Clocking) by using DFT Compiler and TetraMAX on Sophisticated SoC Design
Author(s): Quoc Phan, Vy Tran [Renesas Design]

Strategy to Achieve High Test Coverage for SOC
Author(s): Nor Azura Zakaria [MIMOS Berhad]

Synthesis and Layout Correlation: is DC-Topography the Holy Grail to the Problem?
Author(s): Chuang Shan Chin [Intel Corporation]