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Synopsys Users Group

SNUG Singapore 2007 Proceedings

User Papers and Presentations
User Sessions
Common Platform Synopsys 65nm Reference Flow: Featuring MVDD Design Techniques using ICC
Author(s): Jagan Thinakaran [Chartered Semiconductor Manufacturing] Lydia Lee [Synopsys, Inc.]
Paper Presentation

High Quality Partition Boundary Modeling for Hierarchical Based Design (1st Place - Best Paper)
Author(s): Mr Yew, Edwin Hong Wei, Mr Tee, Kok Tiong [Intel Corporation]
Paper Presentation

Improving Place and Route Flow Efficiency for Complex Design (2nd Place - Best Paper)
Author(s): Teh Eng Keong, Vivian Teh Lin Hwei, Nah Bee Keng, Chin Chuang Shan [Intel Corporation]
Paper Presentation

Novel Methodology for Routability and Timing Optimization on Cross-Clock Domain Design
Author(s): Chin Chuang Shan, Henry Lim Lee Teck [Intel Corporation]
Paper Presentation

Physical Aware Synthesis with DC Topographical
Author(s): Sivaprasad Embanath, Norliza Binti Jalani [MIMOS Berhad]
Paper Presentation

Robust Power Plan Methodology in Astro
Author(s): Darton Huang, Keng Kao, Denny Liu [MediaTek]
Paper Presentation

Variation Aware Statistical Timing Analysis for Nano-CMOS Designs
Author(s): Prashanth Sagar [Chartered Semiconductor Manufacturing Ltd]
Paper Presentation