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Synopsys Users Group

SNUG Singapore 2006 Proceedings

User Papers and Presentations
User Sessions
(What we will probably lose if we don't) Migrate to DFT-Max
Author(s): Teh Chi Chiang [ST Microelectronics]
Paper Presentation

Advanced Atomistic Process and Device Modeling for Optimizing CMOS Devices
Author(s): Yisuo Li, B. Colombeau, F. Bénistant, C. Mok [Chartered Semiconductor Manufacturing], M. Jaraiz [University of Valladolid]
Paper Presentation

Enhancing Defect Limited Yield using Astro/ICC Advance Feature (2nd Place - Best Paper)
Author(s): Shaik Khaja Sharif , Prashanth Sagar [Chartered Semiconductor Manufacturing], Dr. Ara Markosian [Ponte Solutions]
Paper Presentation

Monte Carlo Statistical Analysis for Dynamic Power Simulation of RTL Designs using Synopsys Power Compiler
Author(s): Ravi Kumar Satzoda, Chip-Hong Chang, Thambipillai Srikanthan, [Nanyang Technological University]
Paper Presentation

Power Analysis Flow for SoC
Author(s): Shibu Menon [ST Microelectronics]
Paper Presentation

Power Estimation Methodology using Nanosim
Author(s): Lim Jin Sean, Liu Chin Foon [Intel Corp.]
Paper Presentation

Rapid Static Timing Analysis with ILM
Author(s): Kok Tiong Tee, Aan Chien Tan [Intel Corp.]
Paper Presentation

Routing Avoidance, Analysis and Solving Techniques on Chipset Hierarchical CBD (1st Place - Best Paper)
Author(s): Luck Kuan Tee, Kok Tiong Tee [Intel Corp.]
Paper Presentation

Statistical Modeling for Monte Carlo Simulation using Hspice
Author(s): Kerwin Khu [Chartered Semiconductor Manufacturing]
Paper Presentation