Synopsys Users Group

SNUG Singapore 2005 Proceedings

User Papers and Presentations
User Sessions
Advanced DFM Methodology based on TCAD
Author(s): Francis Benistant, Li Yisuo [Chartered Semiconductor Manufacturing]
Paper Presentation

Analysis of Design Complexity of Datapaths
Author(s): Satzoda Ravi Kumar, Quek Kai Hock, Dr. T. Srikanthan [Nanyang Technological University, Singapore]
Paper Presentation

ASIC Backend Flow using Synopsys Astro
Author(s): Seong Chew, Lim [Integrated Circuit Design Services Sdn. Bhd.]
Paper Presentation

Co-Existing with Legacy Verification Environments in a Vera Testbench
Author(s): Peter Byrne, Kiril Uzunov, Nicholas Aschberger, Bernard Gunther [Australia SoC Technology Centre, Freescale Semiconductor, Adelaide, Australia]
Paper Presentation

Formal Verification in FPGA Synthesis Flow; DC-FPGA & Formality
Author(s): Kee Chun Cheng, Cadman [Creative Technology Ltd]
Paper Presentation

Full Chip Transistor-Level Post-layout simulation and Power Analysis in SoC Design
Author(s): Dong Wei, Lo Han Cheng [Infineon Technologies Asia Pacific Pte. Ltd] Lei Zhang [Infineon Technologies Xi'an Co. Ltd]
Paper Presentation

Ring Oscillator Phase Noise Simulation by Hspice RF
Author(s): Li Yi [FTD Solutions Pte Ltd]
Paper Presentation

Scan Failure Diagnosis using TetraMAX
Author(s): SONG Yun Mei, ZHAO Fang Fang, TAO Ta Wei, MAI Zhi Hong, Benjamin LAU, Jeffrey LAM [Chartered Semiconductor Manufacturing Limited]
Paper Presentation

Uncertainties and Pessimism in PrimeTime/PrimeTime-SI Analysis (1st Place - Best Paper)
Author(s): Sidney Ng, Christophe Bouquet, Anand Shirwal, Siew-Kuan Tham [Infineon Technologies, Singapore]
Paper Presentation

Using Formality to Implement and Verify an ECO Change in an Optimized Netlist (2nd Place - Best Paper)
Author(s): Mark Tang Tuck Houng [O2 Micro Pte Ltd]
Paper Presentation

Using FPGA for Random Verification
Author(s): Andy Chang, Kadambi Ranga, Teo Aik Hwee [Infineon Technologies]
Paper Presentation