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Synopsys Users Group

SNUG San Jose 2009 Proceedings

Complete Proceedings

User Papers and Presentations
For Publication Only
A Complete Verification Solution For Electro-Optical Devices Using Advanced VMM With RAL
Author(s): Zygmunt Pasturczyk, Paul Lungu [Nortel]
Paper

Coverage Driven 1G-Ethernet Switch Verification with Reusable System Verilog Testbench Architecture
Author(s): Yijing Liu, Jenny Yun Guo, Matthew Becker [Freescale Semiconductor Inc.]
Paper

Design Verification and the Designer: Bridging the Gap
Author(s): Theodore Humpal, Vishal Anand [Cisco Systems]
Paper

ECO Hold Fixing using PrimeTime Distributed Multi-Scenario Analysis
Author(s): Hans Kumar [Broadcom Corp.]
Paper

Evaluation of Synopsys's Clock Mesh Technology
Author(s): Troy N. Hicks [Hewlett-Packard Co.]
Paper

Low Power Verification Methodology For DSP Core using SVTB
Author(s): Prashanth Cherukuri [Mediatek Wireless, Inc.]
Paper

MA1 - Design Planning and Timing Constraints
Consistent Timing Constraints with PrimeTime
Author(s): Steve Golson [Trilobyte Systems]
Paper Presentation

Floorplanning and Feasibility Analysis using ICC DP
Author(s): Kritti Pathak [Cisco Systems]
Paper Presentation

MA3 - Statistical Timing (SSTA) and Library Topics
Composite Current Source: Model for Accurate Design Sign Off
Author(s): Purnabha Majumder [NVIDIA Corp.]
Paper Presentation

Variation Aware Analysis using Primetime-VX
Author(s): Arvind N V, Ananth Somayaji, Abhishek Mishra, Ajoy Mandal, Hariprasad TT, Sandeep P, Nicolas Verkinderen, David Colin [Texas Instruments]
Paper Presentation

MA4 - Verification with VMM I
Performance Verification of a Complex Bus Arbiter Using the VMM Performance Analyzer
Author(s): John Dickol, Kari O'Brien [MediaTek Wireless, Inc.]
Paper Presentation

Using the New Features in VMM 1.1 for Multi-Stream Scenarios (Technical Committee Award Honorable Mention)
Author(s): Jason Sprott, Sumit Dhamanwala, JL Gray [Verilab], Clifford Cummings [Sunburst Design Inc.]
Paper Presentation

MB1 - SoC Design
Hierarchical Design Implementation of a Complex SoC Using IC Compiler
Author(s): Young Koog, Harpreet Gill [Samsung Electronics], Tamiko Yoneyama [Synopsys Inc.]
Paper Presentation

Improving Routing QoR, DFM and Runtime at 45 nm with Zroute Technology in IC Compiler
Author(s): Sunil Mehta, Vladimir Yutsis [Advanced Micro Devices], Linda Davidson, Frank Gover [Synopsys, Inc]
Paper Presentation

MB2 - Floorplan-Driven Synthesis Methodology
The Chicken or The Egg: How to Get a Floorplan Before a Netlist
Author(s): Tume Römer [Ericsson AB]
Paper Presentation

Using Design Compiler Topographical to Predict and Alleviate Congestion
Author(s): Dhivakaran Santhanam [Broadcom Corp.], Terry Lee [Synopsys, Inc.]
Paper Presentation

MB4 - Verification Reuse
Bridging the Pre- and Post-Silicon Gap – a Post-Silicon Implementation of Vera for Switch ASIC Verification
Author(s): Kanad Roy [Broadcom, Corp.]
Paper Presentation

Using Bind for Class-Based Testbench Reuse with Mixed-Language Designs (Technical Committee Award Honorable Mention)
Author(s): Doug Smith [Doulos]
Paper Presentation

MC4 - Verification
Optimizing RTL Simulation Performance
Author(s): Scott Fields [NVIDIA Corp.]
Paper Presentation

MC7 - DFM
PrimeYield-LCC-Based Litho-Checking Flow for 40nm IP Design
Author(s): Julia Luo, Tom Mahatdejkul, Swapna Putchala [ARM Inc.], Venkata Battaram, Ron Duncan, Susan Hu [Synopsys]
Paper Presentation

TA2 - Advanced Techniques for Modern Constraints
Simplifying Constraints By Using More Generated Clocks
Author(s): Stuart Hecht [SJH Clear Consulting LLC]
Paper Presentation

Trust Me, I'm Design Compiler! (Synthesis behaviour over varying slack)
Author(s): Philip Watson [ARM, Inc.]
Paper Presentation

TA3 - Parasitic Extraction and Custom Design
Bitcell Extraction for SRAM Design Using Raphael-NXT
Author(s): Tom Mahatdejkul, Ling Chien, Swapna Patchula, Julia Luo, Ing Ming Chang [ARM, Inc.], Missing Venkata Battaram [Synopsys]
Paper Presentation

SBPF Performance and Accuracy Evaluation (Best First-Time Presenter)
Author(s): Dan Prevedel [LSI Corp.]
Paper Presentation

Using NanoTime to Analyze a Digital Memory Interface Logic
Author(s): Yun Mei Lim, Sudheesh Madhavan [Altera Corp.]
Paper Presentation

TA5 - HSIM Simulation
Achieving Increased Simulation Productivity and Accuracy using Star-RCXT Parasitic Extraction and HSIM
Author(s): Shuxian Chen, Ai-Ling Yong, Kostas Pagiamtzis, Sudheesh Madhavan [Altera Corp.], Ravi Krishna Adusumalli [Synopsys]
Paper Presentation

HSIM EM Analysis Integration Flow for Rambus High Speed FlexIO Interface Cell
Author(s): Jason Wei, Vijay Gadde, Ingrid Huang, Chanh Tran [Rambus Inc.], Sumit Vishwakarma [Synopsys]
Paper Presentation

Power and Signal Reliability Using HSIMPlus
Author(s): Satinderjit Singh [ARM, Inc.]
Paper Presentation

TB1 -Design for Low Power
A Predictable Approach to Reducing Clock-Tree Power using IC Compiler Low-Power CTS
Author(s): Hong Li, Narayanan Thondugulam, Santiago Fernandez-Gomez [Apple, Inc.], Shubharthi Datta [Synopsys]
Paper Presentation

Automated Design Flow for Reducing Power in a High Performance Synthesizable Processor Core
Author(s): Arvind Parihar, Avishek Panigrahi [MIPS Technologies], Sharrone Smith [Synopsys]
Paper Presentation

TB4 - Verification Environments & Testbenches I
Attacking Constraint Complexity in Verification IP Reuse
Author(s): Srinath Atluri, Ben Chen, Harish Krishnamoorthy [Cisco Systems, Inc.], Alex Wakefield, Balamurugan Veluchamy, Rebecca Lipon [Synopsys, Inc.]
Paper Presentation

Smart Test Benches for Functional Verification of HDL Using MATLAB and Simulink with VCS Cosimulation and HDL Code Generation
Author(s): Eric Cigan, David Lidrbauch [The MathWorks]
Paper Presentation

TC2 - Low Power Design Methodologies
Design for Power Gating - And What UPF Can, and Cannot, Do for You (Technical Committee Award)
Author(s): David Flynn [ARM, Inc.]
Paper Presentation

Leakage Power Optimization : An Improved Synthesis Methodology
Author(s): Sandip Patra [Broadcom Corp.]
Paper Presentation

TC4 - Verification Environments & Testbenches II
Implementing Layered Stimulus Models Using Implicit Encapsulation
Author(s): Neil Johnson [XtremeEDA Corp.]
Paper Presentation

svunit: Bringing Agile Methods into Functional Verification
Author(s): Bryan Morris, Rob Saxe [XtremeEDA Corp.]
Paper Presentation

TC5 - Mixed-Signal Verification
High Speed Memory Channel Module Verification Using XA Simulator
Author(s): Wen-Hung Lo [NVIDIA Corp.]
Paper Presentation

Mixed Mode Verification of a High-Speed Transceiver with HSIM-VCS Co-Simulation
Author(s): Richard Saito, Ninh Ngo [Altera Corp.]
Paper Presentation

TC6 - AMS - Custom Designer
Applied Common Interfacing Techniques Using OCP
Author(s): Erich Whitney [The MITRE Corp.]
Paper Presentation

WA1 - Aspects of Design Closure
Achieving Antenna-Clean Design Using IC Compiler
Author(s): Ronald Kalim [Consultant], Johnie Au [Cypress Semiconductor]
Paper Presentation

Power Rail Noise Minimization for EMC-Aware Design
Author(s): Patrice Joubert Doriol, Cristiano Forzan, Davide Villa, Davide Pandini, Renato Castellan, Daniele Cervini, Mario Rotigni, Giovanni Graziosi [STMicroelectronics], Giuseppe Contarino, Egidio Marzorati [Synopsys, Inc.]
Paper Presentation

WA2 - Advanced Test Techniques
Breaking the Hierarchy Rules: An Advanced Hierarchical DFT Strategy for a 5 Million Flop Design
Author(s): Charles Njinda [Cisco Systems]
Paper Presentation

Creating an Effective Physically-Aware Test: Data Mining and Test Volume Control
Author(s): Tom Olsen, Someshwar Gatty [Advanced Micro Devices]
Paper Presentation

DFT in Line with the Design: Hierarchical Scan Compression
Author(s): Jianlin Yu, Santiago Fernandez-Gomez [Apple Inc.], Sandeep Kaushik, Aurelia De Colle [Synopsys, Inc.]
Paper Presentation

WA3 - FPGA
Is SystemVerilog Useful for FPGA Design? ("Burn and Learn" versus "Learn and Burn")
Author(s): Stuart Sutherland [Sutherland HDL, Inc.]
Paper Presentation

SoC Emulation in FPGA
Author(s): David Abada [Amicus Wireless Technology Inc.]
Paper Presentation

WA4 - Verification with VMM II
Advanced VMM Transactor Development: Tips for Designing VIP You Wouldn't Mind Reusing (2nd Place - Best Paper)
Author(s): Kelly Larson [MediaTek Wireless, Inc.]
Paper Presentation

An XML-Based Flow for RAL: The Experience of Automating Register Definition from Word Document Specification to VMM Testbench and DUT Implementation for a Home Networking Communication Chip
Author(s): Ritero Chi, Brian Etscheid, Ted Chang [Entropic Communications]
Paper Presentation

WA5 - ESP - CV
Symbolic Simulation for Functional Verification of Embedded Memory Using ESP-CV
Author(s): Hongwei Zhu, Hemant Joshi, Umang Doshi, Rajaram Mouli [ARM, Inc.]
Paper Presentation

Using ESP-CV for Dynamic Power Analysis of Custom Macros to Reduce Analysis Time and Improve Accuracy
Author(s): Stephen Bijansky, Bassam Mohd, Baker Mohammad [Qualcomm]
Paper Presentation

WB4 - Verification with Assertions
If Chained Implications in Properties Weren't So Hard, They'd Be Easy (3rd Place - Best Paper)
Author(s): Don Mills [Microchip Technology]
Paper Presentation

SystemVerilog Assertions - Design Tricks and SVA Bind Files (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.]
Paper Presentation

Tutorials
MA5
Synopsys' Custom Design Solution
Author(s):
Tutorial

MA7
What Designers Need to Know about Full-Chip DFM
Author(s):
Tutorial

MB3
Advanced On-Chip Variation
Author(s):
Tutorial

MB5
Interoperable Process Design Kits for Custom Design
Author(s):
Tutorial

MC1
Zroute: New, DFM-Friendly and Multi-Threaded Routing Technology in IC Compiler
Author(s):
Tutorial

MC2
Accelerating Design Closure
Author(s):
Tutorial

MC4
Introduction to VMM
Author(s):
Tutorial

TA1
Multi-Voltage Implementation Methodology Using UPF
Author(s):
Tutorial

TA4
VMM - Low Power
Author(s):
Tutorial

TA6
Constructing Time Budgets and Improving Timing Margins for DDRn Memory Interface IP
Author(s):
Tutorial

TA7
Incorporating Layout Proximity Effects in Library Characterization
Author(s):
Tutorial

TB2
Techniques for Achieving Higher Completion and Verifying Low Power Designs in Formality
Author(s):
Tutorial

TB3
Faster Timing Closure in a Multi-Scenario World
Author(s):
Tutorial

TB5
Utilizing & Understanding HSIM for Performance & Accuracy Tuning
Author(s):
Tutorial

TB6
Designing High-Speed Serial PHY IP for Chip-To-Chip, Storage and Backplane Applications
Author(s):
Tutorial

TB7
Sign Off-Quality, DRC and Metal Fill Using IC Compiler
Author(s):
Tutorial

TC1
Hierarchical UPF Flow Case Study
Author(s):
Tutorial

TC3
Solving Extraction and Simulation Challenges in SoC Custom Digital/AMS and Memory Designs
Author(s):
Tutorial

TC6
How to Address System-Level Issues in your USB 3.0 Designs
Author(s):
Tutorial

WA6
Achieve Higher Performance and Lower Power Consumption for Mass Storage Designs with SATA Device IP
Author(s):
Tutorial

WB1
Improving RTL-to-GDSII Design Efficiency
Author(s):

WB3
Rapid Multi-FPGA Prototyping: From Project Planning to First-Pass Silicon Success
Author(s):
Tutorial

SCEMI 2.0 Transaction Based Verification with CHIPit
Author(s):
Tutorial

WB5
Learn How to Use New Features in HSPICE 2009.03, Including Statistical Eye Analysis
Author(s):
Tutorial

WB6
Getting 5 Gbps Performance Through 3m of Cable with SuperSpeed USB
Author(s):
Tutorial

WC1
ICC 2008.09 – Highlights
Author(s):
Tutorial

WC2
Galaxy Test: Power-Aware DFT/ATPG and Technical Updates
Author(s):
Tutorial

WC3
Algorithm Implementation and Prototyping Using High-Level Synthesis
Author(s):
Tutorial

WC5
Solving Signal Analysis Challenges with WaveView
Author(s):
Tutorial

WC6
Managing System Bandwidth Requirements with a High-Performance On-Chip Bus
Author(s):
Tutorial