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Synopsys Users Group

SNUG San Jose 2008 Proceedings

User Papers and Presentations
MA1 - Using ICC to Close Timing
Closing the Last Few Picoseconds Using IC Compiler: A 65nm Case Study
Author(s): Sarita Baswant, Umesh Patel [LSI Corp.]
Paper Presentation

Never Let Noise Delay Your Tape-Out
Author(s): Hongda Lu [AMD]
Paper Presentation

MA2 - RTL Synthesis Design Techniques
Fizzim An Open-Source fsm Design Environment
Author(s): Paul Zimmer [Zimmer Design Services], Michael Zimmer [Zimmer Design Services / UCSB], Brian Zimmer [Zimmer Design Services / Zimmertech / UCD]
Paper Presentation

Getting Synchronous Resets Right! (Technical Committee Award)
Author(s): Noah Aklilu [Cisco Systems, Inc.], Anthony Redhead [XtremeEDA Corp.], Pervinder Trehan [Synopsys, Inc.]
Paper Presentation

MA3 - AMS Sign Off
PT-SI vs HSPICE Pushout and Glitch Correlation
Author(s): Louis Tseng [Raza Microelectronics]
Paper Presentation

Using NanoTime for Custom Digital Macros (Technical Committee Award Honorable Mention)
Author(s): Bingxiong Xu, Kevin Stiles [LSI Corp.], Cheung Lam, Louis Andrews [Synopsys]
Paper Presentation

MB2 - Test - Getting the Most out of DFT MAX and TetraMAX
DFT MAX for a Mixed-Signal Design - A Case Study
Author(s): Cory Ellinger [RFMD]
Paper Presentation

Getting to Production on First Silicon Using DFT MAX and TetraMAX
Author(s): Adrian Arozqueta, Christopher Ematrudo [PLX Technology]
Paper Presentation

Small Delay Defect Testing
Author(s): Roberto Mattiuzzo, Saverio Graniello [STMicroelectronics], Salvatore Talluto, Alfredo Conte, Adam Cron [Synopsys, Inc.]
Paper Presentation

MB4 - Practical VMM
Using VMM, DPI and TcL to Leverage Verification to Enable Early Testing, Emulation and Validation
Author(s): Samir Patel [LSI Corp.]
Paper Presentation

Verification of a New IP in Legacy SoC Design using SystemVerilog/VMM
Author(s): Asad Khan, Henry Angulo, David Kimble, Paul Howard [Texas Instruments], Jiri Prevratil, Praveen Devulapalli [Synopsys, Inc.]
Paper Presentation

Verification Patterns in Addition to RVM
Author(s): Carl Cavanagh, Christopher Sine, Lee Warner [Sun Microsystems, Inc.]
Paper Presentation

MB6 - SoC Verification and Validation
Incorporating SystemVerilog and SystemC to Verify Next-Generation Home-Networking Chip
Author(s): Ritero Chi, Ho-Ming Leung, Alex Li [Entropic Communications]
Paper Presentation

Migrating a Large-Scale Vera Testbench Infrastructure to SystemC and SystemVerilog - Risk Mitigation and Value Creation Strategies (1st Place - Best Paper, Best First-Time Presenter)
Author(s): Srinath Atluri, Nimalan Siva, Anant Sakharkar [Cisco Systems Inc.]
Paper Presentation

Virtual Reality for Modem Software Development - Enabling Pre-Silicon Software Development and Validation for 2.5G Wireless Communication
Author(s): Alain Pegatoquet [Texas Instruments], Filip Thoen, Denis Paterson [Synopsys, Inc.]
Paper Presentation

MB7 - AMS
Memory Bitmap Verification Using ESP-CV
Author(s): Jijun Chen [ARM, Ltd.]
Paper Presentation

MC4 - Formal Verification with Magellan
End-to-End Verification of an Arbiter with Magellan
Author(s): Hari Ganesan, Devin Volpe [Sun Microsystems]
Paper Presentation

Verifying MIPS Designs using Magellan
Author(s): Ali Habibi, Jithendra Madala [MIPS Technologies, Inc.], Mandar Munishwar, Haihui Chen [Synopsys, Inc.]
Paper Presentation

MC5 - Verification IP and VMM: Benefits and Real World Experiences
Using Verification IP and VMM Applications to Jumpstart Verification of an AXI Subsystem
Author(s): John Dickol [MediaTek Wireless, Inc.]
Paper Presentation

Verification IP Reuse for Complex Networking ASICs Using a Hybrid SystemVerilog/ SystemC Environment
Author(s): Ben Chen, Srinath Atluri, Harry King [Cisco Systems, Inc.], Shankar Hemmady [Synopsys, Inc.]
Paper Presentation

MC7 - AMS Simulation
Power Measurement Flow for ARM Memory Compilers Using Synopsys HSIMplus
Author(s): Satinderjit Singh [ARM, Ltd.]
Paper Presentation

TA1 - Placement and Layout Optimization Using ICC
A Hierarchical Design Flow for Floorplan and Layout Optimization: A Case Study
Author(s): Santiago Fernandez-Gomez, Monica Nofal [Apple, Inc.]
Paper Presentation

Placement Issues in ICC with Impact on Power
Author(s): Bharat Krishna [Intel Corp.], Nancy Khoury [Syracuse University]
Paper Presentation

TA2 - Low Power Design
Design for State Retention: Strategies and Case Studies (Technical Committee Award Honorable Mention)
Author(s): David Flynn [ARM, Ltd], Alan Gibbons [Synopsys]
Paper Presentation

Power Analysis Methodology: From Spreadsheet to Sign Off
Author(s): George Cuan, Dinesh Patel [Cisco Systems, Inc.]
Paper Presentation

Power-Aware FPGA Design
Author(s): Hichem Belhadj, Vishal Aggrawal, Amal Zerrouki, Ajay Pradhan [Actel Corp.]
Paper Presentation

TA5 - Design Using IP
Methodology for Designing a Power Control Circuit for IP Block
Author(s): Shailja Garg, Sanjay K Sancheti, Anup Nayak [Cypress Semiconductor]
Paper Presentation

TB2 - Design Flows
Closing the Gap Between Synthesis and P&R
Author(s): Madhusudan Kalluri, Kapil Gaba [LSI Corp.]
Paper Presentation

Structured Methods for Delay, Power Tuning and Variation: A Case Study Comparing Relative Placement and Clock Mesh to Standard Placement and Standard Clock Trees on a 90 Nanometer Technology Node Using a Multi-Media Block of ARM's Cortex-A8 Microprocessor
Author(s): Haroon Gauhar, Ashutosh Mujumdar, Stephanie Miller, Dermott O'Driscoll [ARM, Ltd.], Yuichi Kawahara, Mallik Devulapalli, Jason Binney, Tom Chau [Synopsys]
Paper Presentation

TB4 - VMM, RAL, AOP: What Does It All Mean?
A Fully Reusable Register/Memory Access Solution using VMM RAL
Author(s): Paul Lungu, Bo Zhu [Nortel]
Paper Presentation

Techniques for Selective Reuse of Verification Components in Hierarchical Verification of Large Designs
Author(s): Tony Tsai [Cisco Systems, Inc.]
Paper Presentation

TC2- Lower Power Verification
Challenges of Multi-Voltage Verification on a Complex Low-Power Design
Author(s): Sudhakar Ram [NVIDIA], Ajay Krishna, Prapanna Tiwari [Synopsys, Inc.]
Paper Presentation

Low Power Rule Checking Using Leda
Author(s): Shailja Garg, Jason Ferrell, Sanjay K Sancheti, Parthasarathy Narasimhan, Anup Nayak [Cypress Semiconductor]
Paper Presentation

TC3 - Improving Sign Off Accuracy
CCS and NLDM Timing Characterization and Correlation with Liberty-NCX
Author(s): Ronald Kalim [Cypress Semiconductor], Pat Donahue [Synopsys]
Paper Presentation

Fast and Efficient Power Mesh Resistance Calculation Pre-Tapeout Check to Prevent Damaging Circuits During ESD Event
Author(s): Ashish Rajput, Joe Louis-Chandran [Rambus Chip Technology Inc.]
Paper Presentation

TC4 - SystemVerilog Interfacing & Simulation Coverage
Are We There Yet? (2nd Place - Best Paper)
Author(s): Nancy Pratt [IBM], Dwight Eddy [Synopsys, Inc.]
Paper Presentation

Bridging the Application and Design Gap: Utilization of the GDB Proxy Protocol for Remote Control of a VCS Simulation
Author(s): Kelly D Larson [MediaTek Wireless, Inc.]
Paper Presentation

TC6 - Hercules
Addressing Differential Antenna's In Low Voltage SOI Processes Using Hercules
Author(s): Barry O'Connell, Nam Nguyen, Pilar Hsue [National Semiconductor], Lalit Gajare, Elango Velayutham [Synopsys]
Paper Presentation

WA4 - VMM in Practice
OpenVera/RVM to SystemVerilog/VMM Conversion: How to Avoid 'Death By a Thousand Cuts' (3rd Place - Best Paper)
Author(s): Venkata Chintapalli, Dan Steinberg [Integrated Device Technology]
Paper Presentation

Randomized Testbench Development, a Case Study in USB
Author(s): Jason Remple [Broadcom Corp.], Denis Bussaglia, Frederic Krampac [Synopsys, Inc.]
Paper Presentation

Tutorials
MA4
Extract Maximum Value from Your Verification Plan
Author(s):
Tutorial

MA5
Implementing Reliable SoC with DesignWare Clock Domain Crossing IP
Author(s):
Tutorial

MA6
How Open Standards for Transaction-Level Models Can Change the Way You Do Systems Design
Author(s):
Tutorial

MA7
Post-Layout Simulation Methodologies
Author(s):
Tutorial

MB1
UPF Low Power Flow with ARM1176JZF-S Case Study
Author(s):
Tutorial

MB3
NanoTime Increases Design Predictability for Nanometer Applications
Author(s):
Tutorial

MB5
High Speed Design Challenges in DDR3/2
Author(s):
Tutorial

MB7
Simulation Considerations for 45nm Technologies
Author(s):
Tutorial

MC1
Concurrent Hierarchical Design Planning and Implementation Using 2007.12
Author(s):
Tutorial

MC2
Achieving Ultra-High Test Quality Using Galaxy Test Automation
Author(s):
Tutorial

MC3
Star-RCXT, It's Not Just for Gates - Transistor-Level Needs it Too!
Author(s):
Tutorial

MC6
Case Study: Accelerating Software Driver Development for the DesignWare USB HS OTG Core Through Virtual Platforms
Author(s):
Tutorial

TA3
Latest Library Modeling Trends & Liberty NCX
Author(s):
Tutorial

TA4
Advanced VMM - VMM Register Abstraction Layer
Author(s):
Tutorial

TA5
Implementing a 400 MHz Bus Fabric
Author(s):
Tutorial

TA6
Identification and Correction of Design Hotspots using Synopsys PrimeYield and IC Compiler
Author(s):
Tutorial

TA7
What's New in Analog/Transistor Simulation Products
Author(s):
Tutorial

TB3
Getting the Best Performance out of PrimeTime
Author(s):
Tutorial

TB5
Virtualization of PCI Express I/O Devices
Author(s):
Tutorial

TB6
Process-Aware Compact Models for Circuit Variation Analysis
Author(s):
Tutorial

TC1
Implementing Multi-VDD Designs with DCT and ICC
Author(s):
Tutorial

TC5
Selecting the Optimal Embedded Memory Architecture
Author(s):
Tutorial

WA1
Maintain RC Fidelity from RTL to Sign Off at 45nm
Author(s):
Tutorial

WA2
Congestion Prediction and Reduction with Design Compiler
Author(s):
Tutorial

WA5
USB IP: Enabling Lower Power and Smaller SoC Designs
Author(s):
Tutorial

WA6
What Should Designers Know about Manufacturability Issues?
Author(s):
Tutorial

WB1
Usage of ICC Reference Methodology for MCMM and Sign Off Driven Closure
Author(s):
Tutorial

WB2
Design Compiler Family 2007.12 Update
Author(s):
Tutorial

WB4
Functional Coverage Techniques: Leveraging Verification IP and VMM for Efficient Testbenches
Author(s):
Tutorial

WB5
Design Methodologies for Integrating Low Power Interface IP into Ultra-Deep Submicron SoCs
Author(s):
Tutorial

WB6
Model-Based Stress and Lithographic Variation Analysis for 45nm Design and Beyond
Author(s):
Tutorial

WC1
ICC 2007.12 Update
Author(s):
Tutorial

WC4
Synopsys Power Management Verification
Author(s):
Tutorial
Speech
Featured Speaker - Trends in Low Power Design
Author(s): Godwin Maben [Synopsys, Inc.]
Paper

Vision Session - Coping with Variability
Author(s): Narendra Shenoy [Synopsys, Inc.]
Paper

Vision Session - The Future of Low Power - A 2008 Update
Author(s): Mike Keating [Synopsys, Inc.]
Paper