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Synopsys Users Group

SNUG San Jose 2007 Proceedings

User Papers and Presentations
For Publication Only
An EM Verification Flow for Large AMS Designs with StarRCXT and HSIM
Author(s): Wei-Si Jiang [National Semiconductor Corp.]
Paper

MA1 - ICC for Floorplan / Placement
A Systematic Approach to Automated Floorplan Exploration in ICC-DP (65nm)
Author(s): Umesh Patel, Jeff Shi [Agere Systems], Shubharthi Datta [Synopsys, Inc.]
Paper Presentation

Efficient Physical DataPath Specification: Streaming Relative Placement
Author(s): Jeff Dunham, Anand Arunachalam [Synopsys, Inc.]
Paper Presentation

Physical Synthesis for Microprocessor Design
Author(s): Harry H. Yu, Raj Varada [Intel Corp.]
Paper Presentation

MA2 - DFT for SoC
Core Based Test using Scan Compression and Core Isolation
Author(s): Paul Policke [QUALCOMM], Sandeep Kaushik [Synopsys, Inc.]
Paper Presentation

Hybrid Test Methodology for a Multi-Million Gate Design
Author(s): Leah Clark, Amar Guettaf [Broadcom Corp.]
Paper Presentation

MA3 - Delivering DFM - Early, Accurately, Efficiently
Accelerating High Yield Design with Implementation-Stage Lithography Correction
Author(s): Atsuhiko Ikeuchi, Hiroaki Suzuki, Suigen Kyoh, Kyoko Izuha [Toshiba Corp.], Gerard T. Luk-Pat, Alexander Miloslavsky, Frank Tseng, Linni Wen [Synopsys, Inc.]
Paper Presentation

Accurate Lithography Analysis for Yield Prediction
Author(s): Greg Yeric, Babak Hatamian, Rahul Kapoor [Synopsys, Inc.]
Paper Presentation

Smart Density Checking
Author(s): Selvaraj Henry [Intel Corp.]
Paper Presentation

MA4 - Low Power Methodologies
Analyzing Power Integrity on Power Gated Designs
Author(s): Anil Gundurao and Sanjay Sancheti [Cypress Semiconductor]
Paper Presentation

Early Exploration of Multiple Voltage Domains and Activity-driven Clock-gating
Author(s): Udupi Harisharan [Cisco Systems Inc.]
Paper Presentation

Physical and Silicon Measures of Low Power Clock Gating Success: An Apple to Apple Case Study
Author(s): Khem C Pokhrel [Intel Corp.]
Paper Presentation

MA6 - Advanced HSIM Applications in Various Design Flows
Experience of SRAM Design in 65nm/45nm Process
Author(s): Derek Tao, Hans Liao [TSMC]
Paper Presentation

Integration of HSIM-NCverilog and C-code as part of Micron's Simulation Methodology
Author(s): Uday Chandrasekhar [Micron Technology Inc.]
Paper Presentation

Simulation Success with HSIM in Nanometer Design
Author(s): Arvind Vidyarthi [Altera Corp.], Reynaldo Hernandez [Synopsys, Inc.]
Paper Presentation

MA7 - Virtual Platforms and Transaction Level Modeling
System Level Verification: A Case Analysis with Virtio
Author(s): Kalyan Chakravadhanula [Texas Instruments]
Paper Presentation

MB1 - Digital Design
Advantages of Driving DDR Interface Logic at 2x the DDR Clock Versus 1x the DDR Clock
Author(s): Pete Thoeming [Thomson Silicon Components], Ken Umino [Synopsys, Inc.]
Paper Presentation

Design of a 1GHz DSP using IC Compiler
Author(s): Anthony Hill, Mike Gill, Arjun Rajagopal, Todd Beck [Texas Instruments]
Paper Presentation

MB4 - Low Power Design for Higher Performance
Decoupling Capacitance Estimation, Implementation, and Verification: A Practical Approach for Deep Submicron SoCs
Author(s): David Stringfellow, John Pedicone [Synopsys, Inc.]
Paper Presentation

Increasing Designer Productivity with the ARM Cortex-A8 Processor's Rapidly Deployable Synthesizable Implementation
Author(s): Dermot O'Driscoll [ARM Ltd.]
Paper Presentation

MB5 - Practical SystemVerilog I
Gotcha Again - More Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know (2nd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering], Chris Spear [Synopsys, Inc.]
Paper Presentation

Implementation of an AHB Bus Subsystem with SystemVerilog (Technical Committee Award)
Author(s): Eliseu C Filho [Starport Systems, Inc.], Jim Maryoung [Synopsys, Inc.]
Paper Presentation

MC5 - Practical SystemVerilog II
Using SystemVerilog to Ensure a Quality Transition to Randomized Tests
Author(s): John Stubban [Micron Technology]
Paper Presentation

MC6 - HSIM Static Power Net Resistance Analysis
HSIM SPRES: Efficient Powergrid Analysis for Voltage-Drop Problems
Author(s): Huijuan Wang [SanDisk Corp.], Min Guo [Synopsys, Inc.]
Paper Presentation

TA1 - Transitioning from Astro to IC Compiler
ASIC Predictability with Semi-Custom Performance... Is IC-Compiler the Holy Grail?
Author(s): Philip Watson [ARM Inc.], Stephen Edgeworth [Synopsys, Inc.]
Paper Presentation

Migration from Astro to ICC & Achieving Design Closure Using Core Commands
Author(s): Sunil Malkani [Broadcom Corp.], Radhika Shankar [Synopsys, Inc.]
Paper Presentation

Usage of ICC for Concurrent Multi-corner Optimization Technology at AMD
Author(s): Muthukumaravelu Velayoudame, Rainer Mann [AMD]
Paper Presentation

TA4 - Signoff
An Efficient Timing Method for Checking Asynchronous Gray Code Transfers
Author(s): Eric Masson [NVIDIA Corp.]
Paper Presentation

Moving to NanoTime, The Next Generation Transistor Level STA
Author(s): Timothy Raap [Cray Inc.]
Paper Presentation

Where Have all the Phases Gone? Using Multiclock Propagation in PrimeTime (1st Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Paul Zimmer [Zimmer Design Systems]
Paper Presentation

TA6 - Nanosim-VCS Co-Simulation Methodology Flow
Methodology for Co-Simulation of Mixed-Signal IP
Author(s): Jeff McNeal, David A Yokoyama-Martin [Synopsys, Inc.]
Paper Presentation

TA7 - Reusable IP and Methodologies
Automated Tool to Generate Quality Synopsys IP Views
Author(s): Ronald Kalim, Geetha Chigullapalli [Cypress Semiconductor], Joe Varghese, Alpesh Kothari [Synopsys, Inc.]
Paper Presentation

How to Verify and Integrate Mixed Signal Third-Party IP (Best First-Time Presenter)
Author(s): Steven M Waldstein [Tundra Semiconductor], Navraj S Nandra [Synopsys, Inc.]
Paper Presentation

Physical Design and Timing Challenges of a Serial PHY
Author(s): Steve Everley [Everley Consulting, LLC], Ken Umino, Jason Upton, Ross Segelken, John Stonick [Synopsys, Inc.]
Paper Presentation

TB4 - Advanced SI & Variation Aware Signoff
An LLC Timing Sign-Off Model to Cover On-Chip Process Variation
Author(s): Jerry Hong, J D Pan, Peter Pong, Sammy Lee, Simon Ku [Faraday Technology Corp.]
Paper Presentation

Composite Current Source (CCS) Noise Characterization for Standard Cell IP at ARM
Author(s): Neeraj Dogra, Kevin Bui [ARM Inc.]
Paper Presentation

Variation-aware STA Evaluation at QUALCOMM
Author(s): Xin Bao, Alon Ben-Efraim, Ran Lu [QUALCOMM], Elisabeth Moseley [Synopsys, Inc.]
Paper Presentation

TB5 - VMM Environment
Deploying SVTB, VMM and AHB VIP on a New Design
Author(s): Junfeng Wang, YC Wong [Broadcom Corp.], Amir Nilipour, Susan Sien [Synopsys, Inc.]
Paper Presentation

Generating VMM Compliant Environments- A Template Based Approach
Author(s): Dr. Ambar Sarkar [Paradigm Works, Inc.]
Paper Presentation

System Testbench Integration and Reference Verification Methodology: Problems and Solutions
Author(s): David Shleifman [Tundra Semiconductor]
Paper Presentation

TC2 - DFTMax
DFTMax Clinic for Low Power Design
Author(s): Johnie Au [Cypress Semiconductor]
Paper Presentation

Moving to DFTC / DFTMax Flow at QUALCOMM
Author(s): Tsvetomir Petrov, Xiaoyun Sun, Philip Schremmer, Shivakumar Swaminathan, Hyung Lee [QUALCOMM], Paul Micheletti [Synopsys, Inc.]
Paper Presentation

TC5 - VMM Best Practices
Getting the Most Out of Functional Coverage - Tips and Techniques
Author(s): Stephen J. D'Onofrio, Ambar Sarkar [Paradigm Works]
Paper Presentation

Stepping Up to Scenarios in VMM
Author(s): Pierre Girodias, Hans van der Schoot, Amre Sultan [XtremeEDA Corp.]
Paper Presentation

TC6 - HSPICE Advanced SI and Jitter Analysis
PLL Random Jitter Estimation Using Different VCO Phase Noise Simulation Methodologies
Author(s): Metha Jeeradit, Yohan Frans, Reza Navid, Bruno Garlepp [Rambus Inc.]
Paper Presentation

System Level Timing Closure Using HSPICE
Author(s): Todd Westerhoff, Barry Katz [SiSoft]
Paper Presentation

WA2 - DC Topographical / Equivalence Checking
Don't Panic! What to do when Formality Doesn't Give You the "VERIFICATION SUCCEEDED" Message on the First Try. (3rd Place - Best Paper)
Author(s): Leah Clark [Broadcom Corp.], Matt Dittrich [Synopsys, Inc]
Paper Presentation

Evaluation of DC-Topographical
Author(s): Branimir Malnar, Goran Zelic, Santana Lewis, Raghu Raman [Intel Corp.], Craig Maiman [Synopsys, Inc.]
Paper Presentation

Will DCT Really Let Me Get Rid of Wire Load Models? Analysis of a DCT Qualification Effort
Author(s): Chris Kiegle, Maurice Kinney, Chang Suh [IBM], Ray Yock [Synopsys, Inc.]
Paper Presentation

WA5 - High Level Verification
Adopting Hybrid-Formal Methodology for Arbiter Verification
Author(s): Jing Li, Chris Wattana, Mandar Munishwar [Broadcom Corp]
Paper Presentation

Applying CRV to Microprocessor Verification
Author(s): Jason C Chen [Synopsys, Inc.]
Paper Presentation

Verifying Cache Structures with Magellan
Author(s): Thomas J Thatcher [Sun Microsystems]
Paper Presentation

Tutorials
MA5
I Want to Write Assertions Too!
Author(s):
Tutorial

MA7
Transaction Level Modeling - Turbo-charge your Simulation!
Author(s):
Tutorial

MB2/MC2
Test Automation in Galaxy
Author(s):
Tutorial

MB3
Managing Process Variablility for 45nm Designs
Author(s):
Tutorial

MB6
Post-layout Simulation with HSIM
Author(s):
Tutorial

MB7
Software Schedules Dominating Your Time-to-Market? Adopt Virtual Platforms!
Author(s):
Tutorial

MC3
Accelerating Time to Entitled Yield with PrimeYield
Author(s):
Tutorial

MC4
Aggressive Leakage Mitigation in ARM Processor Based Systems
Author(s):
Tutorial

MC6
Demo: HSIMplus Static Power Net Resistance (SPRES) Analysis
Author(s):
Tutorial

TA5
VMM for Dummies
Author(s):
Tutorial

TA6
NanoSim-VCS Mixed-Signal Co-Simulation
Author(s):
Tutorial

TB1
Accelerated Design Convergence with IC Compiler - Concurrent MCMM and Signoff Driven Closure
Author(s):
Tutorial

TB3
Active Yield Management for 65nm and Below
Author(s):

MYM for Faster Yieldramp of New Products
Author(s):
Tutorial

TB6
Simulating Variability in HSPICE
Author(s):
Tutorial

TB7
Analog Design at 65nm
Author(s):
Tutorial

Enabling Rapid Building and Verification of a Complex Sub-system
Author(s):
Tutorial

TC1
Optimizing for Design-Yield with IC Compiler
Author(s):
Tutorial

TC3
Star-RCXT: Improving Simulation Efficiency through Extraction
Author(s):
Tutorial

TC4
Composite Current Source (CCS) Modeling Technology
Author(s):
Tutorial

TC7
DesignWare Floating-point Components: Flexibility to Explore Tradeoffs between QoR and Accuracy
Author(s):
Tutorial

WA1
IC Compiler CTS - Make it Work for You!
Author(s):
Tutorial

IC Compiler Design Planning Reference Methodology (ICC-DP-RM) Exploration Mode: An Automated Approach to Floorplan Exploration and Analysis
Author(s):
Tutorial

WA3
Demystify Variation-aware Design - When You Thought Statistics Was Only for Economics and Theoretical Physics
Author(s):
Tutorial

WA6
Using HSPICE for Signal Integrity Applications
Author(s):
Tutorial

WA7
DDR2-533 and Beyond with DesignWare® Memory Interface IP
Author(s):
Tutorial

WB2 / WC2
Design Compiler and Power Compiler 2007 Update
Author(s):
Tutorial

WB3
PrimeTime PX - Methodology for Power Analysis
Author(s):
Tutorial

WB4
PrimeTime's Distributed Multi-scenario Analysis (DMSA)
Author(s):
Tutorial

WB7
Debugging with Discovery Visualization Environment
Author(s):
Tutorial

WC1
JupiterXT Timing Budgeting
Author(s):
Tutorial

WC4
What's New in Galaxy Low Power 2007.03
Author(s):
Tutorial

WC5
VMM Methodology Techniques for Advanced Users
Author(s):
Tutorial

WC6
Capturing and Analyzing IC Design Productivity Metrics
Author(s):
Tutorial

WC7
Techniques to Achieve Minimum Area with the Synopsys Galaxy Platform
Author(s):
Tutorial