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Synopsys Users Group

SNUG San Jose 2006 Proceedings


User Papers and Presentations
MA2 - SystemVerilog Testbenches
Verifying a Networking ASIC using a SystemC Reference Model and a SystemVerilog Testbench
Author(s): Amit Malhotra [Cisco Systems], Angshuman Saha, Sanjaya Sharma [Synopsys, Inc.]
Paper Presentation

MA3 - Timing Verification Methodologies
A Bottom up Constraint Methodology for use with Hierarchical Designs
Author(s): Noah Aklilu [Cisco Systems]
Paper Presentation

The Last Mile of Physical Design: Timing Closure Loops Between Implementation and Signoff
Author(s): Raghavendra Dasegowda, Paras Gupta [Qualcomm, Inc.]
Paper Presentation

MA4 - Design for Test
Improving Test Quality while Reducing Test Cost using DFT Compiler Max and the DSM Features in TetraMAX ATPG
Author(s): Amar Guettaf [Broadcom Corp.]
Paper Presentation

Squeezing Test Pattern and Pin Counts using DBIST on a 1.5M Gate Device for a Low Cost Test Solution (Technical Committee Award Honorable Mention)
Author(s): Pradeep Atur [Cypress Semiconductor], Paul Micheletti [Synopsys, Inc.]
Paper Presentation

MA5 - DFM with Hercules
Correlating Manufacturing Results and Design Architecture Tradeoffs with Hercules
Author(s): Pallab Chatterjee, Mike Gentry [SiliconMap, LLC]
Paper Presentation

Using Hercules as a Yield Enhancement Tool for Nanometer Designs
Author(s): Huijuan Wang, Michael Wang, Albert Wong, Norman Louie [SanDisk Corp.]
Paper Presentation

TA1 - Backend Flows
Efficient Design Flow for Small Digital, Large Analog Mixed Signal Designs
Author(s): Stephen Lin, Venkat Kowkutla [Texas Instruments Inc.]
Paper Presentation

Hierarchical Astro-Rail Analysis of a One-billion-transistor, Full-custom Design
Author(s): Jia-Lih Chen, Thierry Lemeunier, Dustin Do, Sudheesh Madhavan, Yaron Kretchmer [Altera Corp.]
Paper Presentation

TA3 - Vendor Session: Enhancing Productivity with Third-Party Tools
Electronic System Level (ESL) Debug -- Trends, Requirements, and Technology
Author(s): Bindesh Patel, Harish Poojary [Novas Software]
Paper Presentation

Power Optimization in FPGA Designs
Author(s): Mouzam Khan [Altera Corp.]
Paper Presentation

TA6 - IP
High Speed Serial Interconnects - What to Look for When Selecting an IP Vendor
Author(s): Boris Litinsky [RF Microdevices], Navraj Nandra [Synopsys, Inc.]
Paper Presentation

Integrating DesignWare Digital IP Core for PCI Express into Agere's ET1310 Gigabit Ethernet Controller
Author(s): Fadi Saibi [Agere Systems], Jing-fan Zhang [Synopsys, Inc.]
Paper Presentation

TB2 - Verification I
Creating a VMM Compliant Verification Plan
Author(s): Ambar Sarkar [Paradigm Works]
Paper Presentation

VMMing a SystemVerilog Testbench by Example (Technical Committee Award)
Author(s): Ben Cohen [VhdlCohen Publishing], Srinivasan Venkataramanan, Ajeetha Kumari [Independent]
Paper Presentation

TB3 - Experiments and Experiences with SystemVerilog and SystemC
A SystemVerilog Class Template for Finite State Machine Design
Author(s): Swapnajit Mitra [Project VeriPage Inc.]
Paper Presentation

An Integrated SystemC/Verilog RTL Simulation Infrastructure for Co-simulation of ESL Models
Author(s): David Goldberg [Synfora Inc.]
Paper Presentation

TC2 - RVM
Getting off the Ground when Creating an RVM Testbench
Author(s): Rich Musacchio, Ning Guo [Paradigm Works Corp.]
Paper Presentation

Integrating System Models in an RVM Leveraged Environment
Author(s): Anand Acharya [Qualcomm], Shaun Evans [Synopsys, Inc.]
Paper Presentation

TC3 - Design Transformation Pitfalls Revealed
Physical Layer Verification for PCI Express (3rd Place - Best Paper)
Author(s): Dan Steinberg [Integrated Device Technology]
Paper Presentation

TD3 - Getting the Most out of Magellan - Using SVA Constraints and Setup Tricks
How to Get your REALLY Difficult Properties Proven
Author(s): Thomas Thatcher [Sun Microsystems]
Paper Presentation

SystemVerilog Constraints for Assertion-based Formal Verification
Author(s): Hanif Perwad [SGI], Mandar Munishwar [Synopsys, Inc.]
Paper Presentation

WA1 - Floorplanning and Physical Design
1.2 - 1.5+ M Instances Flat Design for 0.13um Process
Author(s): Steve Doan, Koshi Matsushita, Chien-yeh Wu, Srini Burugu [Synopsys, Inc.]
Paper Presentation

Floorplanning a Multi-Million Instance Design with JupiterXT's Virtual Flat Methodology
Author(s): Xin Chang, Jessica Zhang [Via/S3 Graphics], Antonio Dimalanta [Synopsys, Inc.]
Paper Presentation

WA2 - Assertions Based Verification
Assertion Based Checkers for Serial Protocols: Special Considerations
Author(s): Monika Talwar, Jitendra Puri [nSys Design Systems Pvt Ltd.], Soumen Basak [Synopsys, Inc.]
Paper Presentation

PSL |=> SVA: A Case Study in The Use of Assertions, and The Power of SVA (Technical Committee Award Honorable Mention)
Author(s): Al Czamara [LOA Technology]
Paper Presentation

SystemVerilog Assertions are for Design Engineers Too! (2nd Place - Best Paper)
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering]
Paper Presentation

WA3 - Techniques for Solving Unique Design Challenges
Automated FFT RTL Creation using Verilog with Matlab and Perl
Author(s): John Kuhns, Cole O'Berry, Richard Hayden [Synopsys, Inc.]
Paper Presentation

Automated FFT RTL Creation using Verilog with Matlab and Perl
Author(s): John Kuhns, Cole O'Berry, Richard Hayden [Synopsys, Inc.]
Script

Oh, Synchronous Reset!
Author(s): Linming Jin [Brocade Communication Systems], Leo Butler [3Leaf Networks]
Paper Presentation

Solving Timing Convergence Problems in High Performance Processor Designs
Author(s): Zia Khan, Imtiaz Hussain,Nelson Chan [Intel Corp.]
Paper Presentation

WA4 - Verification II
Digital Simulation of Multi-Power Well Designs using PLI
Author(s): Uri Segal [SMSC]
Paper Presentation

Leda Use in Industry: Design Quality Improvements and Proprietary System Integration
Author(s): Scott Vento [IBM Systems and Technology Group], Raymond Yock [Synopsys, Inc.]
Paper Presentation

Using SystemVerilog Testbench for High Level Behavioral Modeling of a SIMD Processor Design (Best First-Time Presenter)
Author(s): Shankar Govindaraju, Jayanto Minocha, Kevin Rich, David Dobrikin [Transmeta Corp.]
Paper Presentation

WA5 - Libraries and Modeling
Automatic MilkyWay Technology File Generation
Author(s): Ronald Kalim, David John [Cypress Semiconductor], Sridhar Panchapakesan, Liang Xu [Synopsys, Inc.]
Paper Presentation

Basic Characterization Analog IP
Author(s): Peter Chen, Harrison Liu, Peter Pong, Jim Wang, K.C. Wu, Alvin Chen, David Chen [Faraday Technology Corp.]
Paper Presentation

Timing Sign-off using CCS Libraries at QUALCOMM
Author(s): Xin Bao, Khusro Sajid [Qualcomm, Inc.], Elisabeth Moseley [Synopsys, Inc.]
Paper Presentation

WA6 - Advanced Timing Analysis
An Automated Methodology for Systematic Analysis of the Timing Impact of Cells with Tied Input Pins
Author(s): Vishwas Rao, Stephanie Lam Alter [Agere Systems]
Paper Presentation

Critical Paths Verification and Debugging with PrimeTime Advanced Features (1st Place - Best Paper)
Author(s): Wei-Si Jiang [National Semiconductor]
Paper Presentation

Getting DDRs 'write' - the 1x Output Circuit Revisited (1st Place - Best Paper)
Author(s): Paul Zimmer [Zimmer Design Services]
Paper Presentation

Tutorials
MB1
Clock Gating and Hierarchical Timing Views (HTV) in Your Design
Author(s):
Tutorial

MB4/MC4
Test Automation in Galaxy (dark background
Author(s):
Tutorial

Test Automation in Galaxy (white background for printing)
Author(s):
Tutorial

MB7
Galaxy Reference Flow
Author(s):
Tutorial

MC1
Improving Design Yield
Author(s):
Tutorial

MC2
Advanced SystemVerilog Coverage Metrics with VCS and Magellan
Author(s):
Tutorial

MC3
Improving Accuracy with PrimeTime and PrimeTime SI
Author(s):
Tutorial

MC5
Test Chips for DFM and Litho Impact on Design (dark background)
Author(s):
Tutorial

Test Chips for DFM and Litho Impact on Design (white background for printing)
Author(s):
Tutorial

TB1
Getting Started With IC Compiler
Author(s):
Tutorial

TB4
Tapeout Proven UMC-Synopsys 90nm Reference Flow
Author(s):
Tutorial

TB5
Synthesis without Wire-load Models (dark background)
Author(s):
Tutorial

Synthesis without Wire-load Models (white background for printing)
Author(s):
Tutorial

TB6
Building an Application Interface for PCI Express: A Case Study using AXI (dark background)
Author(s):
Tutorial

Building an Application Interface for PCI Express: A Case Study using AXI (white background for printing)
Author(s):
Tutorial

TC5
High-Performance Subsystem Design using AMBA™ 3 AXI (dark background)
Author(s):
Tutorial

High-Performance Subsystem Design using AMBA™ 3 AXI (white background for printing)
Author(s):
Tutorial

TD1
The IC Compiler GUI: Introduction and Benefits (dark background)
Author(s):
Tutorial

The IC Compiler GUI: Introduction and Benefits (white background for printing)
Author(s):
Tutorial

TD2
Transaction-Level Modeling in an Integrated SystemC/SystemVerilog Environment (dark background)
Author(s):
Tutorial

Transaction-Level Modeling in an Integrated SystemC/SystemVerilog Environment (white background for printing)
Author(s):
Tutorial

TD4
Abutted, Hierarchical Floorplans Using JupiterXT
Author(s):
Tutorial

TD5
Vital Steps to a Robust Testbench with DesignWare VIP and RVM (dark background)
Author(s):
Tutorial

Vital Steps to a Robust Testbench with DesignWare VIP and RVM (white background for printing)
Author(s):
Tutorial

WA7
DCmatch Analysis in HSPICE (dark background)
Author(s):
Tutorial

DCmatch Analysis in HSPICE (white background for printing)
Author(s):
Tutorial

WB2
Using the Verification Methodology Manual (VMM) for SystemVerilog to Deliver Measurable, Comprehensive, Productive and Reusable Verification
Author(s):
Tutorial

WB4
Designing with Synopsys Power Portfolio in Galaxy (dark background)
Author(s):
Tutorial

Designing with Synopsys Power Portfolio in Galaxy (white background for printing)
Author(s):
Tutorial

WB5
How to Add Wireless USB to Your Wired USB Design (dark background)
Author(s):
Tutorial

How to Add Wireless USB to Your Wired USB Design (white background for printing)
Author(s):
Tutorial

WB6
Modeling for Advanced Interconnect Designs (dark background)
Author(s):
Tutorial

Modeling for Advanced Interconnect Designs (white background for printing)
Author(s):
Tutorial

WB7
Improve First-pass Silicon Success using NanoSim and NanoSim-VCS (dark background)
Author(s):
Tutorial

Improve First-pass Silicon Success using NanoSim and NanoSim-VCS (white background for printing)
Author(s):
Tutorial

WC1
An Automated Approach to Floorplan Exploration and Analysis using JupiterXT
Author(s):
Tutorial

WC3
Composite Current Source (CCS) Modeling Technology
Author(s):
Tutorial

WC4
Automated Setup Files: Flow Simplification and Advanced Technology for Arithmetic and Retimed Designs (dark background)
Author(s):
Tutorial

Automated Setup Files: Flow Simplification and Advanced Technology for Arithmetic and Retimed Designs (white background for printing)
Author(s):
Tutorial

WC5
Dynamic Voltage-drop and EM Analysis for Low Power Designs with PrimeRail (dark background)
Author(s):
Tutorial

Dynamic Voltage-drop and EM Analysis for Low Power Designs with PrimeRail (white background for printing)
Author(s):
Tutorial

WC6
Datapath Design Techniques (dark background)
Author(s):
Tutorial

Datapath Design Techniques (white background for printing)
Author(s):
Tutorial

WC7
HSIMplus CircuitCheck and Applications
Author(s):
Tutorial