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Synopsys Users Group

SNUG San Jose 2005 Proceedings

User Papers and Presentations
MA1 - Verification I
A Practical Experience with VCS Native Testbench on a Real World Design
Author(s): Jang Dae Kim, Sonny Datta [National Semiconductor Corp.]
Paper Presentation

Integrating Verilog Testbench into an NTB Environment
Author(s): Qing Lou [nVidia Corp.]
Paper Presentation

PCI Bridge Verification with Concurrent Stimulus Threads on a Reusable Testbench Architecture
Author(s): Hugo Cavalcanti, Walter Encinas, Cesar Duenas [Freescale Semiconductor]
Paper Presentation

MA2 - Deep Submicron Floorplanning and ECO Techniques
Floorplanning Principles
Author(s): Richard Rodgers [Agilent Technologies]; Kevin Knapp and Chris Smith [Synopsys, Inc.]
Paper Presentation

Interactive and Incremental ECOs
Author(s): Malcolm White [Corrent Corp.]
Paper Presentation

Single Mask Layer Programming
Author(s): Malcolm White [Corrent Corp.]
Paper Presentation

MA3 - Low Power Design
Estimating Dynamic Power for a Multi-Million Gate Wireless LAN ASIC
Author(s): Subbu Meiyappan, Derrick Lin [Airgo Networks Inc.]
Paper Presentation

Fight the Power - Power Reduction Ideas for ASIC Designers and Tool Providers (3rd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Serag GadelRab, David Bond, David Reynolds [Tundra Semiconductor]
Paper Presentation

Reducing Gate Count and Power with Power Compiler
Author(s): William Leavitt [Emulex Corp.]
Paper Presentation

MA4 - Design Analysis using PrimeTime
Extending PrimeTime
Author(s): Colin MacDonald [Freescale Semiconductor]
Paper Presentation

Working with PLLs in PrimeTime (Technical Committee Award)
Author(s): Paul Zimmer [Zimmer Design Services]
Paper Presentation

MA5 - Extraction and Process Migration
A Practical Approach to Process Corner Models of Interconnect RC Extraction
Author(s): Wei-Si Jiang [ National Semiconductor Corp.]
Paper Presentation

Numerical Analysis of Parasitic Effects in Deep Submicron Technologies
Author(s): Cole Zemke [IBM Corp.] and Jitendra Lagu, Kevin Brelsford [Synopsys, Inc.]
Paper Presentation

Using Hercules as a Probe for Design Intent Based Custom IP Migration
Author(s): Pallab Chatterjee, Michael Gentry [SiliconMap, LLC]
Paper Presentation

R&D Panels
MB5/TA5/WC5 - IC Compiler: Physical Implementation Roadmap to the Future
Author(s): Donald Friedberg [Agere Systems], Anthony Hill [Texas Instruments], Jean-Pierre Geronimi [STMicroelectronics], Philip Watson [ARM]
Presentation

TC1 - Verification II
SystemVerilog Saves the Day-the Evil Twins are Defeated!, unique and priority are the new Heroes
Author(s): Stuart Sutherland [Sutherland HDL Inc.]
Paper Presentation

The Bumpy Road of Progress: Transitioning to a SystemVerilog-based Simulation Environment for Embedded ASIC Verification
Author(s): Won Rhee [Agilent Technologies]
Paper Presentation

Using OpenVera Assertions to Verify PCI Express Protocol
Author(s): Ravindra Viswanath [LSI Logic Corp.] and Srikanth Vijayaraghavan [Synopsys, Inc.]
Paper Presentation

TC4 - Signal Integrity
Methodology to Close Timing on All Corners with Synopsys Galaxy at and Below 130nm
Author(s): Atif Hussain [Texas Instruments, Inc.] and Ken Umino [Synopsys, Inc.]
Paper Presentation

PrimeTimeSI Qualification at TI: A case study
Author(s): Shailendra Dhuri, Rajagopal KA, Deepak Vohra, Arvind NV, Madhurima Ghose [Texas Instruments, Inc.]
Paper Presentation

TC5 - Signal Integrity
Lessons Learned from an IP Reuse Project: a View from the RTL Design and Verification Trenches
Author(s): Kevin Thompson [Cypress Semiconductor]
Paper Presentation

Power Estimation and Thermal Management in FPGA Design
Author(s): Phil Simpson [Altera Corp.]
Paper Presentation

Using ASIC Prototyping to Reduce Risks
Author(s): King Ou [Altera Corp.]
Paper Presentation

TD1 - Formal Verification Techniques
99 Bottles of Formality on the Wall…
Author(s): Matt Weber [Silicon Logic Engineering]
Paper Presentation

Working Formal Verification Backwards to Validate your RTL Functions
Author(s): Matthew Noell [Raytheon]
Paper Presentation

TD3 - System Level Verification Environments
Augmenting a C++/PLI/VCS Based Verification Environment with SystemC
Author(s): Ambar Sarkar [Paradigm Works Inc.]
Paper Presentation

Verification of a Mixed Signal ASIC Using SystemVerilog with MATLAB and the DPI
Author(s): Ron Shipp [Synopsys, Inc.]
Paper Presentation

TD4 - Clock Tree Design
Effects of Specialized Clock Routing on Clock Tree Timing, Signal Integrity and Routing Congestion (Best First-Time Presenter)
Author(s): Jesse Craig [IBM Corp.], Denise Powell [Synopsys, Inc.]
Paper Presentation

Methodology to Achieve Stringent Clock Skew Specifications using Astro CTS
Author(s): Rakesh Mehrotra, Bo Gao [Cypress Semiconductor]
Paper Presentation

WA1 - Verification III
Using Vera in the Lab (Technical Committee Award Honorable Mention)
Author(s): K.C. Buckenmaier, Jie Ding, Changyong Yang [Hifn] and Chris Spear [Synopsys, Inc]
Paper Presentation

Verification of GeForce 6800 GPU with VCS Simulation and Hammer Hardware Acceleration
Author(s): Ramesh Narayanaswamy - Tharas Systems and Narendra Konda -- nVidia Corp.
Paper Presentation

WA2 - The Memory Works: DFT Testing and Symbolic Verification
Embedded Memory Testing With DFT Compiler
Author(s): Harish Dangat [Cypress Semiconductor]
Paper Presentation

Low-Power Memory Verification using Symbolic Simulation
Author(s): Vidyadhar Vuppula [Qualcomm Inc.], David Hedges [Synopsys, Inc.]
Paper Presentation

WA3 - Mixed-Signal Verification
Hybridization Methodology for Finding Maximum Capacitance of Mixed Signal Design
Author(s): Peter Chen, Steven Chien, Sam Lee, Harrison Liu, Jim Wang [Faraday Technology]
Paper Presentation

Mixed-Signal Design and Verification, Static or Dynamic? (1st Place - Best Paper)
Author(s): Johnie Au [Cypress Semiconductor]
Paper Presentation

SCRIPTS: Mixed-Signal Design and Verification, Static or Dynamic?
Author(s): Johnie Au [Cypress Semiconductor]
Script1

SCRIPTS: Mixed-Signal Design and Verification, Static or Dynamic?
Author(s): Johnie Au [Cypress Semiconductor]
Script2

WA4 - Power Integrity and Analysis
A Hierarchical Rail Analysis Flow for Multimillion Gate SoCs - Challenges and Solutions
Author(s): Hamid Piroozi, Krishna Gopinathannair [Thomson Multimedia Inc.], Ted Bernard, David Stringfellow [Synopsys, Inc.]
Paper Presentation

Methodology to Perform Rail Analysis at a Very Early Stage of the Design using AstroRail
Author(s): Kenneth Egan [Xemi], Hani Saleh, Michael Solka [Synopsys, Inc.]
Paper Presentation

WA5 - Hierarchical Physical Design
Physical Compiler Unlimited
Author(s): Bo Gao, Rakesh Mehrotra [Cypress Semiconductor]
Paper Presentation

WB1 - Verification III
A Practical Guide to Adopting Synopsys' Reference Verification Methodology
Author(s): Neil Johnson, Ian Perryman, Branko Petrovic [Altera Corp.]
Paper Presentation

Tips on Verifying a PCI-Express Design with Hydrid Formal Verification – Magellan
Author(s): Dejian Li [VIA Technologies Inc.], Jenny Zhang [Synopsys, Inc.]
Paper Presentation

WB4 - On-Chip Variation
Modeling IR Drop and other OCV Effects in PrimeTime
Author(s): Anis Jarrar, Kirk Taylor [Freescale Semiconductor]
Paper Presentation

The ABOVE (Angle Based On-Chip Variation Estimation) Technique for a Process Variation-Prone Design
Author(s): Rasit Topaloglu [University of California] and Dennis Lau, Hosam Haggag [National Semiconductor Corp.]
Paper Presentation

WB5 - Hierarchical Physical Design
Physical Datapath: Regularized Datapath Placement and Optimization Technology (2nd Place - Best Paper)
Author(s): Anthony Hill, Duc Bui, Todd Kroeger [Texas Instruments Inc.] Anand Arunachalam [Synopsys Inc.]
Paper Presentation

Programmable Shield Ring Generation for Hierarchical Physical Design
Author(s): Yigang Sun, Jenny Gong [Qualcomm Inc.]
Paper Presentation

WC3 SCRIPT
HSPICE with Verilog-A and Productivity Boosts and Automating Waveform Analysis in CosmosScope
Author(s):
Script

Tutorials
MB2
Extraction Challenges and Solutions for Analog/Mixed Signal Designs
Author(s):
Tutorial

MB3
Galaxy RTL Synthesis Update (dark background)
Author(s):
Tutorial

Galaxy RTL Synthesis Update (white backgound (for printing)
Author(s):
Tutorial

MB4
AMBA 2 Based Subsystem Design in a Jiffy (dark background)
Author(s):
Tutorial

AMBA 2 Based Subsystem Design in a Jiffy (white background for printing)
Author(s):
Tutorial

MC1
Getting the Most out of VCS Native Testbench
Author(s):
Tutorial

MC2
Structured Methodology to Code Common Runset for LVS Verification and Extraction Flows
Author(s):
Tutorial

MC3
Multi-Voltage Design Implementation: The Leading-Edge Technique for Low Power Management (dark background)
Author(s):
Tutorial

Multi-Voltage Design Implementation: The Leading-Edge Technique for Low Power Management (white background for printing
Author(s):
Tutorial

MC4
RTL Coding Guidelines for Datapath Synthesis
Author(s):
Tutorial

TA1/TB1
Getting Started with the Reference Verification Methodology (dark background)
Author(s):
Tutorial

Getting Started with the Reference Verification Methodology (white background for printing)
Author(s):
Tutorial

TA2
High-End FPGA Design: Reality or Oxymoron? (white background for printing)
Author(s):
Tutorial

High-End FPGA Design: Reality or Oxymoron? (dark background)
Author(s):
Tutorial

TA3
Physical Compiler 2004.12 Highlights (white background for printing)
Author(s):
Tutorial

Physical Compiler 2004.12 Highlights (dark background)
Author(s):
Tutorial

TA4
Galaxy Test Solutions: DFT Compiler and TetraMAX Updates (white background for printing)
Author(s):
Tutorial

Galaxy Test Solutions: DFT Compiler and TetraMAX Updates (dark background)
Author(s):
Tutorial

TB3
Astro CTS for Better QoR (dark background)
Author(s):
Tutorial

Astro CTS for Better QoR (white background for printing)
Author(s):
Tutorial

WC1/WD1
SystemVerilog Assertion: Best Practices for Functional Verification (dark background)
Author(s):
Tutorial

SystemVerilog Assertion: Best Practices for Functional Verification (white background for printing)
Author(s):
Tutorial

WC2/WD2
JupiterXT Advanced Topics (dark background)
Author(s):
Tutorial

JupiterXT Advanced Topics (white background for printing)
Author(s):
Tutorial

WC3
HSPICE with Verilog-A and Productivity Boosts and Automating Waveform Analysis in CosmosScope (white background for printing)
Author(s):
Tutorial

HSPICE with Verilog-A and Productivity Boosts and Automating Waveform Analysis in CosmosScope (dark background)
Author(s):
Tutorial

WC4/WD4
PrimeTime & PrimeTime SI Technology Update
Author(s):
Tutorial