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SNUG India 2009 Proceedings

Complete Proceedings

User Papers and Presentations
AMS
Custom Macro Characterization and STA Using Nanotime
Author(s): Basudeva Dash, Amit Didwania, Vineet Puri [Infineon Technologies]
Paper Presentation

Performance Evaluation of Statistical Eye Simulation (StatEye) in HSPICE for Backplane Systems
Author(s): Sivagurunathan, Sam David, Pramitha [Wipro Technologies]
Paper Presentation

Power Management & Behavioral Model Checks in Co-simulations Using VCSMX-NANOSIM Tool
Author(s): Ashwin Nyamati, Rajeev Suvarna, Ravi Kumar Reddy [Wipro Technologies]
Paper Presentation

SPICE Level Verification of Full Chips When Digital Verification is Just Not Enough!
Author(s): Sandip Atal, Fabio Carlucci, Ashish Kumar Gupta, Rohitaswa Bhattacharya, Luca Buratti [ST Microelectronics], Rakesh Shenoy [Synopsys]
Paper Presentation

SRAM Compilers Timing Analysis Using Active-Net Based HSIM-Star-RCXT Flow (1st Place - Best Paper, AMS)
Author(s): Gaurav Varshney, Dharin Shah, Parvinder Rana, Sateesh Chandramohan [Texas Instruments India Pvt Ltd]
Paper Presentation

Synopsys HSPICE Based Automatic Standard Cell Circuit Generation
Author(s): Lakshmi Jain, Niharika Kishore, Nimmida Abdulsalam, Sunitha S [Wipro Technologies]
Paper Presentation

Using "Divide and Conquer" to Address Tight Deadlines of Electromigration Flow
Author(s): Atul Bhargava, Bharat Bhushan, Neeraj kapoor, Tushar Sharma [ST Microelectonics]
Paper Presentation

XA: A Case Study of PLL and ADC Verification
Author(s): Premraj Rajasekharan Nair, Lakshmi Govindankutty [Wipro Technologies]
Paper Presentation

FPGA/IP
Efficient Emulation Methodology of Multi-Million Gate SoCs Using Synopsys FPGA Tools (1st Place - Best Paper, FPGA)
Author(s): Sabyasachi Dey, Praveen Goyal, Ankit Srivastava [Qualcomm India Pvt. Ltd.]
Paper Presentation

Prototyping of SoC Design for Wireless USB applications on HAPS-54 Platform
Author(s): Subramanian Parameswaran, Manish Kumar Saxena, Jagonda Balgonda Patil [Samsung India Software Operations]
Paper Presentation

Verifying Complex SoCs Using FPGA Based Prototypes
Author(s): Vijay Chachra [LSI India Pvt Ltd]
Paper Presentation

Physical Design
A Comprehensive Flow for the Implementation of Large and Complex Multimedia Designs in 45nm and Beyond (1st Place - Best Paper, Physical Design)
Author(s): Sreeram Chandrasekar, Aishwarya Singh, Gowrysankar Shanmugam, Anup Rajput, Amitesh Khongal [Texas Instruments India]
Paper Presentation

A Pseudo-Hierarchical Place and Route Flow Approach to Handle Design Disparities
Author(s): Raashid Shaikh, Santhosh T, Arathy M [Texas Instruments India Pvt Ltd], Anshuman Anand [Synopsys, Inc.]
Paper Presentation

Advanced Implementation techniques for closing timing critical processor using ICC
Author(s): Deepti Miyan, Ashish Khurana [ST Microelectronics]
Paper Presentation

Best-in-class Clock Tree Power on a 45nm High Density TI IP
Author(s): Hari Krishnamoorthy [Texas Instruments India Pvt Ltd], Harissh Swaminathan [Synopsys, Inc.]
Paper Presentation

Cost Efficient Implementation of High Performance, Low Power Designs
Author(s): Ravishankar B, Vithal Ambi, Ravneet Singh [LSI India Pvt Ltd], Subrata Kumar Sen [Synopsys, Inc.]
Paper Presentation

Evaluating ICC-DP as a FloorPlanning for a Complex Hierarchical Design
Author(s): Maria Martin, Srinivas P, Sridevi Warrier [Analog Devices India Pvt. Ltd.]
Paper Presentation

Implementation of ARM® Mali™- 400 MP Graphics Processor Using MIM and ILM of Synopsys Galaxy Platform
Author(s): Vikram Kuralla [ARM Embedded Technologies Pvt. Ltd.]
Paper Presentation

Routing at Advance Process Nodes to Improve DFM/Yield, QoR, Power, Runtime Using ICC Zroute
Author(s): Pradeep Kothari, Praful Gaikwad [AMD India Pvt Ltd], Kodur Narsimha Reddy [Synopsys, Inc.]
Paper Presentation

Signoff
An Approach to Hierarchical Multi-Voltage Noise Analysis Using PT-SI with Minimal Runtime-Accuracy Tradeoff (1st Place - Best Paper, Sign-Off)
Author(s): Chakradhar Tallury, Vijay Kumar Budumuru, Vijaykishan Narayanan [AMD India Pvt Ltd]
Paper Presentation

CCS Flow for Accurate Timing/Noise Closure for 65nm and Below
Author(s): Raghavendra.V [Open-Silicon]
Paper Presentation

Challenges and Solutions Towards 40nm Timing and Reliability Signoff
Author(s): Rajagopal KA, Vidit Babbar, Ashwini Gopinath, Palkesh Jain, Ajoy Mandal, Prateek Thakyal, Prashant Soraiyur [Texas Instruments India Pvt Ltd]
Paper Presentation

Comprehensive and Accurate Capacitance Extraction Solution Using Star-RCXT/Raphael-NXT
Author(s): Nischal S, Ashwini Gopinath, Shailendra Dhuri, Pankaj Goinka, Arvind NV [Texas Instruments India Pvt Ltd]
Paper Presentation

Methodology to Deal With UITE-461 for Clock Dividers
Author(s): Azad Singh [ST Microelectronics]
Paper Presentation

Methodology to Verify and Debug the Quality and Completeness of Constraints
Author(s): Sujit Jadhav [LSI India Pvt Ltd], Vikas Choudhary [Synopsys, Inc.]
Paper Presentation

Signoff Crosstalk Noise Analysis Using PTSI - A Methodology Perspective
Author(s): Gopinath Venkatesh, Prashant Soraiyur, Rajagopal K.A, Vidit Babbar [Texas Instruments India Pvt Ltd]
Paper Presentation

Synthesis
Accelerating Design Closure using DC-Graphical and ICC
Author(s): Suresh Raman, Srivatsa Srinath [Intel Technologies India Pvt]
Paper Presentation

Congestion Prediction and Optimization Using Design Compiler Graphical
Author(s): Jayesh K Vijayan, Rajani D, Praveen Kothanath [Wipro Technologies]
Paper Presentation

Fanout and Statistical Power Estimation based Minimal Scan Cell Gating for Low Test Power Consumption (1st Place - Best Paper, Synthesis)
Author(s): Vishwanath.S, Mohammed Ashfaq Shukoor, Srinivas Kumar Vooka, Srivaths Ravi [Texas Instruments India Pvt Ltd]
Paper Presentation

Synthesis Of Ultra High Performance Designs
Author(s): Budumuru Vijay Kumar, Chakradhar Tallury, Shyam Jagini, Arun Iyer [AMD India Pvt Ltd]
Paper Presentation

Synthesis Strategy Trend of Current SoCs: Practices and Challenges
Author(s): Mayank Jindal, Deepak Saraff, Sarveswara Tammali, Manasi Gokhale [Texas Instruments India Pvt Ltd]
Paper Presentation

Synthesis Techniques for Formal Equivalence Closure in Timing Critical Designs
Author(s): Ashish Mishra [Qualcomm], Anantha Bhat [Synopsys, Inc.]
Paper Presentation

Verification
Approach to Verifying a Design for Robustness to Errors in a Constrained Random SV/VMM Environment
Author(s): Kauser Rabbani, Manikandan Chandrasekaran, Atul Kalambur [Nvidia Graphics Pvt. Ltd.]
Paper Presentation

Assertion-Based Verification of Mixed-Signal Behaviors with Sampling Clock
Author(s): Subhankar Mukherjee, Subrat Panda. Pallab Dasgupta [IIT Kharagpur]
Paper Presentation

Autogeneration of Config Generator, Transactor, SV Assertions and Coverage From Register Specification
Author(s): Ravitej Sriram, Ashish S Hegde [Nvidia Graphics Pvt. Ltd.]
Paper Presentation

Coverage Driven Verification Environment For WLAN MAC System: A VMM Based Approach
Author(s): Joice George, Praveen S R, Shilpa Prakash, Vasudev Srinivasan [Wipro Technologies]
Paper Presentation

Designing Low Power WLAN Chips - The UPF Way
Author(s): Venkateshwarlu V [Redpine Signals, Inc]
Paper Presentation

DFT Verification Flow Improvements - Needs and Results
Author(s): Prasanth V, Rajesh Kedia, Milan Shetty, Srihari Mallavarappu [Texas Instruments India Pvt Ltd]
Paper Presentation

Faster Verification Closure Using VMM and DesignWare VIP's
Author(s): Anup Aprem, Sajeev Thomas [Analog Devices Pvt. Ltd.]
Paper Presentation

Gate Level Verification of Multi-Voltage Design
Author(s): Ravi Kanth Aluru, Sambhav Jain, Ashis dash [Nvidia Graphics Pvt. Ltd.], Vishwanath Sundararaman [Synopsys]
Paper Presentation

Guided Convergence Towards Verification Closure Using VMM Planner
Author(s): Pritpal Singh Hira, Amarjeet [Freescale Semiconductors], Mayank Digvijay [Synopsys, Inc.]
Paper Presentation

Hierarchical System Level Test Bench Development Using VMM - SV
Author(s): Shankar. S, Syed Sheeraj. G, Venkata Suresh, Babu. M, Murali Krishna. A [Cypress Semiconductor Ind Pvt Ltd]
Paper Presentation

HW-FW co-simulation using SystemVerilog TestBench
Author(s): Vikram Bichal, Srinivas Reddy B, Sridhar Kotha [Brocade Communications]
Paper Presentation

Improving Verification Quality & Confidence of a Bridge Design Using Assertion IP's and Hybrid Formal tool Magellan
Author(s): Aneet Agarwal, Divya Dhiran [Texas Instruments India Pvt Ltd]
Paper Presentation

Methodologies for Complex SOC Verification
Author(s): Pradeep Babu, Rahul Maitra [Texas Instruments India Pvt Ltd], Prathamesh Joshi [Synopsys, Inc.]
Paper Presentation

Multi Voltage CPU Design Verification - Power Intent Extraction Flow
Author(s): Balakrishna Mohan Kanukollu, Veera Pradeep Pasupuleti [AMD India R&D Centre Private Limited]
Paper Presentation

Multi Voltage Verification for High End Mobile Processor Design
Author(s): Jianfeng Liu [Samsung Electronics]
Paper Presentation

RTL and Verification Challenges and Changes for Low Power Design Verification Using MVSIM
Author(s): Narasimha Karunakar, Harpreet Arora [AMD India Pvt Ltd], Vikram Malik [Synopsys, Inc.]
Paper Presentation

Verifying Complex Low Power Integrated Graphics Chip: A Methodology Using MVSIM and MVRC (1st Place - Best Paper, Verification)
Author(s): Girish Kumar S, Alok Jain [Nvidia Graphics Pvt. Ltd], Sesha Sai Kumar C V, A. Krishna Theja [Synopsys, Inc.]
Paper Presentation

Tutorials
AMS
Synopsys' Custom Design Solution
Author(s):
Tutorial

Utilizing & Understanding HSIM for Performance & Accuracy Tuning
Author(s):
Tutorial

FPGA/IP
Hardware Assisted Verification Techniques
Author(s):
Tutorial

Physical Design
Clock Mesh in IC-Compiler
Author(s):
Tutorial

Hierarchical Flow/Clock Tree Mesh Updates
Author(s):
Tutorial

IC Compiler Design Planning Highlights
Author(s):
Tutorial

Signoff
Advanced On-Chip Variation
Author(s):
Tutorial

Lynx - Improving RTL to Design Efficiency
Author(s):
Tutorial

Synthesis
Accelerating Design Closure
Author(s):
Tutorial

Techniques for Achieving Higher Completion and Verifying Low Power Designs in Formality
Author(s):
Tutorial

Verification
VMM - Low Power
Author(s):
Tutorial