HOME    COMMUNITY    SYNOPSYS USERS GROUP
Synopsys Users Group

SNUG India 2007 Proceedings

User Papers and Presentations
Physical Design and Sign-off
Accurate Gate-Level Power-Estimation in Primetime-PX using Vectors Generated from RTL Simulation
Author(s): Shitanshu Tiwari, Soumya N, Kalpesh Shah [Texas Instruments]
Paper Presentation

Achieving Aggressive Design Goals for High Performance Wireless Applications using IC Compiler
Author(s): Mamatha Jayanth, Kartik Ayyar [Qualcomm]
Paper Presentation

Challenges in Crosstalk-Aware Hierarchical STA for Multi-Million Gate VoIP SoC (1st Place - Best Paper, Physical Design and Sign-Off)
Author(s): Aakash Agrawal, Subrangshu Das, Shailendra Dhuri, [Texas Instruments]
Paper Presentation

Concurrent Multi-Mode Optimizations and Multi-Supply Flow with ICC Empowers to Fight the Evils of Design
Author(s): Anil Yadav, [ST Microelectronics]
Paper Presentation

Dynamic IR Drop Sign-off Analysis using Prime Rail
Author(s): Deepak Kumar Arora, Abhay Kumar, Jwalant Joshipura, RakeshShenoy Panemangalore, [ST Microelctronics]
Paper Presentation

Implementing a High Performance 65nm Core using ICC
Author(s): Balasubramanian Rajeswaran, [Texas Instruments]
Presentation

Increased Designer Productivity for ARM Cortex-A8 Processors
Author(s): Roma Kundu, Manmohan Loganathan [ARM Embedded Technologies Pvt. Ltd.]
Paper Presentation

Managing Timing Convergence Efficiently in a Mixed Design Methodology
Author(s): Anupam Rajoria, Satishchandra G Rao, [Analog Devices]
Paper Presentation

Multimode Multiscenario Analysis on IP Designs
Author(s): Ananth Somayaji, [Texas Instruments]
Paper Presentation

Physical Verification Throughput Improvement for Very Large SoCs in Sub-Wavelength Regime
Author(s): Dibyendu Goswami, Swami Gangadharan, [Intel]
Paper Presentation

Timing and Noise Analysis Accuracy with CCS Models
Author(s): Viswanath Ramanathan, Pavan Kumar Kaipa, [Intel]
Paper Presentation

Poster Session
Adding Whistles to Synopsys Tools using Tcl
Author(s): Puneet Goel, Ashis Maitra [Transwitch]
Paper

Methodology for Hierarchy Separation at Asynchronous Clock Domain Boundaries for Multivoltage Optimization using Design Compiler
Author(s): Alok Anand, Sajish Sajayan [Texas Instruments]
Paper

Verifying an Image Processing System using VMM
Author(s): Ajeetha Kumari, S Naresh Kumar, Govind Bagath Singh V [Contemporary Verification Consultants Pvt Ltd.]

Synthesis & Test
A Novel ILM Based SoC Synthesis Strategy Using Unified Constraints
Author(s): Soujanna Sarkar, Paresh Joshi, Vasudev Sinari, [Texas Instruments]
Paper Presentation

Collaborative and Innovative DFT for "Pushing-the-envelope" Designs
Author(s): C. P. Ravikumar [Texas Instruments], Mohammed Hussain, Sumitha Krishnamurthi [Synopsys]
Paper Presentation

Concurrent Fault Detection: The New Paradigm for Compacted Test Vectors
Author(s): Srinivasulu Alampally, Srinivas Kumar Vooka [Texas Instruments], Jais Abraham, Satish Panigatti [InnoDes Solutions Pvt. Ltd]
Paper Presentation

Correlation of Synthesis and Layout: Is DC-T the Solution?
Author(s): V. Parimala, [Texas Instruments]
Paper Presentation

DC-Topographical for Structured-ASIC
Author(s): Varun Jindal, [ST Microelectronics]
Paper Presentation

Dynamic Shift Frequency Scaling Of ATPG Patterns (1st Place - Best Paper, Synthesis and Test)
Author(s): Aditya Ramachandran [Open-Silicon Research Private Limited]
Paper Presentation

Hierarchical Adaptive Scan Synthesis for Multi-Million Gate Designs
Author(s): Prasanna Kaliamoorthy, Kapil Kothari, [Open-Silicon Research Private Limited]
Paper Presentation

How Formal Verification can Become Bottleneck After Successful Synthesis?
Author(s): Swapnil Bahl, Atul Arora, Sabyasachi Das, Mohinder Vij [ST Microelectronics]
Paper Presentation

Increased Designer Productivity for ARM Cortex-A8 Processors
Author(s): Roma Kundu, Manmohan Loganathan [ARM Embedded Technologies Pvt. Ltd.]
Paper Presentation

Physical Aware Synthesis with DC Topographical
Author(s): Sivaprasad Embanath [MIMOS Berhad]
Paper Presentation

Small Delay Defect Testing in DSM Technologies- Needs and Considerations
Author(s): Srinivasulu Alampally, Prasanth V, Rajesh Tiwari, Sumitha Krishnamurthi, [Texas Instruments]
Paper Presentation

Verification & AMS
A High-Performance Timing Simulation Methodology for Multi-Processor SoCs
Author(s): Bhaskar J Karmakar, Ish Dham, Sivaprasad Acharya [Texas Instruments]
Paper Presentation

A Methodology for Generating Interface Timing Models of Complex Custom Designs using Nanosim & Star RC
Author(s): Satishchandra Rao, Vijaykishan N, Vinoth Kumar, Jayakrishnan V, Srijith Varma [Analog Devices]
Paper Presentation

An Efficient Approach for Verifying a Pipelined Processor
Author(s): Manmohan Singh, Srikanth Muralidharan, Sunil Parmar, V. Ranjith Kumar, Praneet Dixit [Qualcore Logic]
Paper Presentation

Analysis of Sustainable Wait Latencies for a Host Interface Module using Magellan
Author(s): Prasenjit Basu, Raj S Mitra, Sarbadipta Datta [Texas Instruments]
Paper Presentation

Complex Signal Integrity Simulations for GPIOs using HSIM Hierarchical Flow (1st Place - Best Paper, AMS)
Author(s): Rakesh Sawant, Nagarathinam Senthil [Qualcomm]
Paper Presentation

Constraint Based Random Verification Methodology for the Generic Designs
Author(s): Swapnil Sapre, Hitesh Kumar Mishra [Freescale]
Paper Presentation

Functional Verification of SPI3 TX Link Core using VMM
Author(s): Ramamohan Sriram, Shreedevi C, Archana Gupta, Debajyoti Mukherjee [Wipro Technologies]
Paper Presentation

Multiple Voltage Domains Testing Using Functional Simulation
Author(s): Sukruth Pattanagiri, Sivakumar R [Analog Devices]
Paper Presentation

RAL Demystified: A Fast Path to Smart Control Plane Verification
Author(s): Gaurav Jain, Yogesh Mittal, Parag Goel [Transwitch]
Paper Presentation

Spice Acceleration by Introduction of HSIM in Design Cycle for Analog Circuits
Author(s): Anuj Gupta [ST Microelectronics], Rakesh Shenoy [Synopsys]
Paper Presentation

Usage of VMM to Address Gigabit Switch Verification Challenges (1st Place - Best Paper, Verification)
Author(s): Yogesh Mittal, Neeraj Chandak, Parag Goel [Transwitch]
Paper Presentation

VMM Based Verification Environment for Telecom Designs
Author(s): Paul Kaunds, Sowmya Sullia,Asha Rai [Kacper Technologies]
Paper Presentation

Tutorials
Tutorials
Accelerated Design Convergence with IC Compiler Concurrent MCMM and Signoff Driven Closure
Author(s):
Tutorial

Composite Current Source (CCS) Modeling
Author(s):
Tutorial

DDR2-533 and Beyond with DesignWare Memory Interface IP
Author(s):
Tutorial

Debugging with Discovery Visualization Environment
Author(s):
Tutorial

Design Compiler 2007 Update
Author(s):
Tutorial

Enabling Rapid Building and Verification of a Complex Sub-system
Author(s):
Tutorial

Post-layout Simulation with HSIM
Author(s):
Tutorial

PrimeTime PX - Methodology for Power Analysis
Author(s):
Tutorial

PrimeTime's Distributed Multi-Scenario Analysis (DMSA)
Author(s):
Tutorial

Software Schedules Dominating Your Time-to-Market? Adopt Virtual Platforms!
Author(s):
Tutorial

Star-RCXT: Improving Simulation Efficiency through Extraction
Author(s):
Tutorial

Techniques to Achieve Minimum Area with the Synopsys Galaxy Platform
Author(s):
Tutorial

Test Automation in Galaxy
Author(s):
Tutorial

VMM Methodology Techniques for Advanced Users
Author(s):
Tutorial

What's New in Galaxy Low Power 2007.03
Author(s):
Tutorial