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Synopsys Users Group

SNUG Boston 2008 Proceedings

User Papers and Presentations
MA1- RTL/SystemVerilog Coding Practices for Synthesis
Building Polymorphic Modules with Synthesizable SystemVerilog Constructs
Author(s): Brian Hook [Analog Devices, Inc]
Paper Presentation

The Ten Commandments of RTL Coding
Author(s): Eric Ryherd [Cypress Semiconductor]
Paper Presentation

MA2 - Advancements in Routing
Improving Routing QoR, DFM and Runtime at 45nm with Zroute Technology in IC Compiler
Author(s): Sunil Mehta, Vladimir Yutsis [Advanced Micro Devices, Inc.], Linda Davidson, Frank C. Gover [Synopsys, Inc.]
Paper Presentation

MA3 - Multi-Simulation Environments
Porting Legacy Verification Environment to SystemVerilog Based Testbenches for Complex Optical Networking SoC
Author(s): Darshan Sheth, Nilesh Ranpura [eInfochips]
Paper Presentation

Using Cosimulation of MATLAB and Simulink with VCS in a Functional Verification Environment (Best First-Time Presenter)
Author(s): Eric Cigan, David Lidrbauch [The MathWorks, Inc.]
Paper Presentation

MB1 - Easing Physical Design Challenges during Synthesis and Power Analysis
A Systematic Analysis of the Correlation Between DC-T and ICC
Author(s): Vishwas Rao, J.C. Parker [LSI Corporation], Thomas Wilderotter [Synopsys, Inc.]
Paper Presentation

DC Graphical: The Promise and the Reality (Technical Committee Award Honorable Mention)
Author(s): Philip Watson [ARM, Ltd.], Tom Fairbairn [Synopsys, Inc.]
Paper Presentation

Hybrid Approach to Power Analysis
Author(s): Pankaj Aggarwal, Rashedul Islam [Tensilica Inc.]
Paper Presentation

MB2 -Low Power and Hierarchical Implementation
A User's Experience in Developing a Low Power Flow with UPF
Author(s): Colm O'Doherty, Alan Whooley, Brian Coffey [Analog Devices, Inc.]
Paper Presentation

A Utility for Leakage Power Recovery within PrimeTime-SI (Technical Committee Award Honorable Mention)
Author(s): Bruce Zahn [LSI Corporation]
Paper Presentation

MB3 - Advanced Verification Special Topics
Constraint Solver Diagnostics
Author(s): Henrik Scheuer [Advanced Micro Devices, Inc.], Alex Wakefield [Synopsys, Inc.]
Paper Presentation

Reducing Failing Testcase Length: Mixing Brute-Force and Intelligence to Extract Meaningful Information from Many Simulations (2nd Place - Best Paper)
Author(s): Jonathan Wolfe [MediaTek Wireless, Inc.]
Paper Presentation

Verifying a Challenging Processor Core Using Magellan
Author(s): Tushar Ringe [Analog Devices, Inc.]
Paper Presentation

MB4 - AMS Simulation with HSPICE and HSIM
HSIMplus CircuitCheck on Mixed-Signal Power-Management Designs: A Life-Saver
Author(s): Vincent Bligny [STMicroelectronics]
Paper Presentation

W-Element and S-Parameter Models for High Speed Board Traces - Do We Need Both?
Author(s): Johann Nittmann, Scott Meninger [Cavium Networks]
Paper Presentation

MC3 - SystemVerilog Tips and Techniques
Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.]
Paper Presentation

Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas (3rd Place - Best Paper, Technical Committee Award)
Author(s): Shalom Bresticker [Intel Corporation]
Paper Presentation

MC4 - User Experiences with XA
Acceleration of Analog Simulations with Synopsys XA
Author(s): Larissa Nitchougovskaia [Advanced Micro Devices, Inc.]
Paper Presentation

XA Integration in Custom Power MOSFET Analysis Flow
Author(s): Giuseppe Greco [STMicroelectronics], Claudio Rallo [Synopsys, Inc.]
Paper Presentation

TA1 - Test in the Modern World
Case Study - Physical Impact of Scan and Compression
Author(s): Ralph Jankowich [Qualcomm], Howard Gainey, Brad MacMonagle [Synopsys, Inc.]
Paper Presentation

TetraMAX ATPG Power-Aware Results on the ARM Cortex™-A8 Microprocessor
Author(s): Frank Frederick, Teresa L. McLaurin [ARM Inc.]
Paper Presentation

User Experience with Small Delay Defect ATPG
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro [TranSwitch Corporation], Mona Marmash [Synopsys, Inc.]
Paper Presentation

TA2 - Physical Design/Sign Off
Accurate Timing Closure with Voltage Aware STA
Author(s): Anil Gundurao, Ali Eltoukhy [Cypress Semiconductor]
Paper Presentation

Unintentional Forward Biased Diode Checker
Author(s): Arnold Baizley, Joe Iadanza [IBM Corporation]
Paper Presentation

TA3 - VMM in Action
Applying VMM to the Verification of an Industrial Control Design
Author(s): Iman Abdo, Ryan Yuan Chen [Patni Americas]
Paper Presentation

Dealing with Inexactitude in VMM Verification
Author(s): Joseph Manzella [LSI Corporation]
Paper Presentation

Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM
Author(s): Heedo Jung [Samsung Electronics Co.], Aditya Kher [Synopsys, Inc.]
Paper Presentation

Tutorials
MA2
The Future of Routing in IC Compiler - Zroute
Author(s):
Tutorial

MB2
Hierarchical Design Planning in IC Compiler
Author(s):
Tutorial

MB4
Fast and Accurate Eye Data Generation with HSPICE
Author(s):
Tutorial

MC1
Removing Congestion with Design Compiler
Author(s):
Tutorial

TA2
IC Compiler 2008.09 Layout Editing Demo
Author(s):
Tutorial

TA4
Technical Insight into SoC Prototyping using FPGAs
Author(s):
Tutorial

TB1 / TC1
Achieving Ultra-High Test Quality: Timing and Power-Aware ATPG
Author(s):
Tutorial

TB2
Physical Design Update
Author(s):
Tutorial

TB3
Constraint Diagnostics and Guidelines
Author(s):
Tutorial

TB4
Improving Design Efficiency from Concept to Final FPGA Implementation with ESL Design and Physical Synthesis
Author(s):
Tutorial

TC2
Getting the Best Performance out of PrimeTime
Author(s):
Tutorial

TC3
Creating Reusable Testbenches Using Scoreboards and Partitioned Environments
Author(s):
Tutorial

TC4
Modern Optimization and Verification Strategies for Complex FPGA Designs
Author(s):
Tutorial

Speech
Vision Session
Coping with Variability
Author(s): Narendra Shenoy [Synopsys, Inc.]
Paper

The Limits of Compression
Author(s): Dr. Thomas W. Williams [Synopsys, Inc.]
Paper