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Synopsys Users Group

SNUG Boston 2007 Proceedings

User Papers and Presentations
MA1 - Constrained Random, Functional Coverage and Verification Techniques
A SystemVerilog Coverage Driven Test Generator for Processor Design Verification (Technical Committee Award Honorable Mention)
Author(s): David Brownell, Tushar Ringe [Analog Devices]
Paper Presentation

Advanced Random Constraints to Manage the Data Flow of a Packet Memory
Author(s): John Stiles [Silicon Logic Engineering, Inc.]
Paper Presentation

Customizing VMM to Add Global Progress Management
Author(s): Boone Severson, John Thompson [Cray Inc.], Tyler Bennett [Synopsys, Inc.]
Paper Presentation

MA2 - Synthesis Strategies and Evaluation of DC-Topographical
Evaluating the Benefit of DC Topographical to the Entire Design Flow
Author(s): Shane Keating, David Lamb [Analog Devices], John Geremia [Synopsys, Inc.]
Paper Presentation

Evaluation of DC-Topographical
Author(s): Branimir Malnar, Santana Lewis, Goran Zelic, Raghu Raman [Intel Corp.], Craig Maiman [Synopsys, Inc.]
Paper Presentation

Winner-Take-All Optimization for Design Synthesis
Author(s): Kapil Gaba [Agere Systems], Christopher Rose [Synopsys, Inc.]
Paper Presentation

MA3 - ICC Success Stories
Breaking the Gigahertz Speed Barrier with an Automated Flow Using Commercial Standard Cell Libraries and Memories
Author(s): Soumya Banerjee, Avishek Panigrahi [MIPS Technologies], Dan Lefrancois, Sharrone Smith [Synopsys, Inc.]
Paper Presentation

Success with MCMM
Author(s): Jeff Shi [LSI Corp.], Sohail Siddiqui [Synopsys, Inc.]
Paper Presentation

MA4 - Static Timing for Post-layout and Custom Circuits
Bottoms-Up Hierarchical Timing Budgeting using PrimeTime
Author(s): Duane Galbi, Ranjit Loboprabhu, Christopher McGlone [Intel Corp.]
Paper

Hold Me Please! How to Fix Post-Route Hold Violations Quickly and Easily Using Distributed Multi-Scenario Analysis
Author(s): Dwight Galbi [Analog Devices, Inc.], Beth Herman, Brandon Waldo, Mike Castellano, Chris Papademetrious [Synopsys, Inc.]
Paper Presentation

Static Timing Analysis on Custom Circuits at the 65nm Technology Node and Beyond, Can NanoTime Cut You Some Slack?
Author(s): Lakshmikant Mamileti [Qualcomm], Patrick Donahue [Synopsys, Inc.]
Paper

MA5 - Analog Mixed Signal
Efficient Full-Chip Verification of STMicroelectronics Smart Power Applications with HSIM-NCSim Co-Simulation Methodology
Author(s): Branimir Ivetic, Claudio Vignati, Lyes Djama [STMicroelectronics], Carlo Borromeo [Synopsys, Inc.]
Paper Presentation

Multi-Gigabit Serial Link Analysis - Piecing Together a Design and Verification Strategy
Author(s): Michael Steinberger, Todd Westerhoff [SiSoft]
Paper Presentation

MB1 - Verification Using VMM Methodologies and Techniques
A VMM Based Generic Interrupt Handling Mechanism
Author(s): Ning Guo, Rich Musacchio, Steve D'onofrio, Ambar Sarkar [Paradigm Works]
Paper Presentation

Creating Stimulus and Stimulating Creativity: Using the VMM Scenario Generator (2nd Place - Best Paper)
Author(s): Jonathan Bromley [Doulos Ltd.]
Paper Presentation

MB3 - Final Physical Finishing
From Validation to Generation: Making Hercules do the Heavy Lifting (Best First-Time Presenter)
Author(s): Dale Donchin [Analog Devices, Inc.]
Paper Presentation

Multiphase Flow for Meeting Metal Density and Gradient Requirements at 65nm
Author(s): Jim Dodrill, Dwight Galbi [Analog Devices, Inc.], Moheb Basta, Mike Castellano [Synopsys, Inc.]
Paper Presentation

TA1 - Design & Debug using SystemVerilog
Finding A Tricky IP Bug With SVA (A Real World Example)
Author(s): Paul McGaugh [Broad Reach Engineering, Inc.], David Castle [Synopsys, Inc.]
Paper Presentation

SystemVerilog Implicit Port Enhancements Accelerate System Design & Verification (1st Place - Best Paper)
Author(s): Clifford Cummings [Sunburst Design, Inc.]
Paper Presentation

TA2 - DFT Techniques for Yield Enhancement
Failure Data Gathering and Analysis for Yield Enhancements of a COT Manufacturer
Author(s): Zahi Abuhamdeh, Vincent D'Alessandro, Bob Hannagan [TranSwitch], David Chagnon [Synopsys, Inc.]
Paper

Power Management During Test on the ARM Cortex-A8 Microprocessor
Author(s): Teresa L McLaurin [ARM Inc.], Glenn Boyer, Lori Schramm, Don Skinner [Synopsys, Inc.]
Paper Presentation

TA3 - Floorplan Challenges
Highly Rectilinear Digital Place and Route Challenges Solved by Astro
Author(s): Eric Ryherd [Cypress Semiconductor]
Paper Presentation

Honey, I Shrunk the Die. Don't Worry, the Kids are OK.
Author(s): Jonathan Bahl [COT Consulting, Inc.]
Paper Presentation

When Floorplans Attack: How To Balance Routing, Timing and Area on Problematic Designs (Technical Committee Award)
Author(s): John Vargas [Unisys], Peter Jarvis [Synopsys, Inc.]
Paper Presentation

TA4 - Low Power Prediction and Implementation
Advanced Low Power, Multi-Supply Implementation Techniques for 65nm and Beyond using DCT and ICC
Author(s): Dwight Galbi [Analog Devices], Brandon T Waldo [Synopsys, Inc.]
Paper Presentation

Complex Rectilinear Floorplan and Implementation for Multi-Voltage Domain, Low Power ASICs
Author(s): Govindarajan Natarajan, Shankar NG, Ramakrishna Alluri, Venkateswra Rao Arumilli, Zameer Ahmed, Seshagiri TN, Neel Das [Tallika Corp.]
Paper

Moving to the "Next" Technology Node
Author(s): Jim Vanaria, Paul Pua [TranSwitch Corp.]
Paper Presentation

TA5 - System-Level SOC Validation
The Diagnostic Channel: Increasing Visibility and Control in SystemC Models
Author(s): Joseph Chapman [The MITRE Corp.]
Paper Presentation

Using SystemVerilog DPI to Create Comprehensive Hardware/Software Co-Verification Environments
Author(s): Alicia Strang, Pei-hsiu Suen [Marvell Semiconductor, Inc.]
Paper Presentation

TB4 - IR Drop
Full Chip IR Drop Methodology for Low Power Applications
Author(s): Shailja Garg, Sanjay K Sancheti, Anup Nayak [Cypress Semiconductor]
Paper Presentation

IR Drop Analysis of a 65nm Complex Power-Gating Design: Issues and Solutions
Author(s): Michael Allen, Dwight Galbi, Joe Geisler [Analog Devices], Kaijian Shi, Julio C Hernandez [Synopsys, Inc. ]
Paper Presentation

TB5 - Tips to Integrate and Verify Reusable IP
The Ten Edits I Make Against Most IP (3rd Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Wilson Snyder [SiCortex, Inc.]
Paper Presentation

Tutorials
MA3
ICC Signoff Optimization
Author(s):
Tutorial

MA5
Think Differential, it's a Mixed-Mode World
Author(s):
Tutorial

MB2
Techniques to Achieve Minimum Area with the Synopsys Galaxy Platform
Author(s):
Tutorial

MB4
How (and Why!) To Use PrimeTime's Distributed Multi-Scenario Analysis
Author(s):
Tutorial

MB5
Overcoming Mixed-signal Verification Challenges with NanoSim and VCS
Author(s):
Tutorial

MC1
Coverage Analysis and Convergence with Synopsys Discovery Platform
Author(s):
Tutorial

MC2
Migrating Your Synthesis Methodology to Design Compiler Topographical
Author(s):
Tutorial

MC4
Composite Current Source Modeling Technology
Author(s):
Tutorial

PrimeTime VX
Author(s):
Tutorial

MC5
Star-RCXT, It's Not Just for Gates - Transistor-Level Needs It Too
Author(s):
Tutorial

TA5
Transaction-Level Modeling - Turbo Charge your Simulation!
Author(s):
Tutorial

TB1
Getting the Best Performance with VCS and the Discovery Platform
Author(s):
Tutorial

TB2
Test Automation in Galaxy
Author(s):
Tutorial

TB3
Reference Methodologies for IC Complier and IC Compiler Design Planning
Author(s):
Tutorial

TC1
Reusing Legacy Components in VMM
Author(s):
Tutorial

TC2
Augmenting Design Rule Checking with Lithography Compliance Checking
Author(s):
Tutorial

TC3
Accelerated Design Convergence with IC Compiler - Concurrent MCMM
Author(s):
Tutorial

TC4
UPF Featuring Synopsys' Power Management Solution
Author(s):
Tutorial

TC5
DesignWare Memory Interface IP Takes You to the Next Frontier - DDR3
Author(s):
Tutorial

Tutorial White Paper - MC1
Coverage Analysis and Convergence with Synopsys Discovery Platform
Author(s):
Tutorial

Tutorial White Paper - TB1
VCS Compilation Options to Maximize Performance
Author(s):
Tutorial

Tutorial White Paper - TC1
Reusing Legacy Components in VMM
Author(s):
Tutorial