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Synopsys Users Group

SNUG Boston 2006 Proceedings

User Papers and Presentations
MA1 - SystemVerilog Testbench
Avoiding Polymorphism Pitfalls... or How to Build an Extendable Verification Environment
Author(s): Nancy Pratt, Santoshkumar Jinagar, Divya Jayasree, Jesse Craig [IBM]
Paper Presentation

Directed ro Random: A Verification Methodology Shift Using SystemVerilog Testbench Constructs
Author(s): Kelly Larson [Analog Devices, Inc.]
Paper Presentation

MA2 - SoC Power Techniques
Aggressive Leakage Management in ARM Based Systems (3rd Place - Best Paper)
Author(s): John Biggs [ARM], Alan Gibbons [Synopsys, Inc]
Paper Presentation

Methodology to Analyze and Insert a Power Mesh Early in Design Cycle
Author(s): Joseph Schrand [Thomson Silicon Components], Ken Umino [Synopsys, Inc.], Evan Chen [Synopsys,Inc.]
Paper Presentation

Power Reduction Through Channel Length Optimization and Clock Gating using Power Compiler - An SoC Case Study
Author(s): Duane Galbi, Ranji Loboprabhu, David Lewis [Intel Corp]
Paper Presentation

MA3 - Physical Design Analysis and Techniques
Integration of a data path generation with an ASTRO flow
Author(s): Kossay Omary, Sunny Shin [C2 Micro], Marwan Ashkar, Fuad Abu Nofal [Nova]
Paper Presentation

Multi-corner Yield Management Analysis - Running Corners that Guarantee Yield using Synopsys Backend Tools
Author(s): Ranjit Loboprabhu, Duane Galbi, Christopher Mcglone [Intel Corp]
Paper Presentation

Taming the "Congestion" Beast - Methods to Handle Congestion during Physical Design Implementation
Author(s): Nghi Huynh [Qualcomm, Inc], Lavanya Murugesan [Synopsys, Inc]
Paper Presentation

MA4 - PrimeTime
Analysis of Accuracy vs. Runtime/Memory Tradeoffs in PrimeTime SI
Author(s): Jason Dowling, Beth Herman [Synopsys, Inc]
Paper Presentation

Budget Timing Constraint Generation by Post-Processing PrimeTime Results
Author(s): Terry Biggs, Amjad Qadan, Matt Stefaniw [Hewlett Packard]
Paper Presentation

Using DMSA to Dramatically Improve the ECO Flow
Author(s): Jayaram Bhasker [eSilicon Corp.], Pete Jarvis, Chris Papademetrious [Synopsys, Inc]
Paper Presentation

MA5 - IP Implementation and Verification Methodology
Automated Response Generation for IP Based Subsystem Verification
Author(s): Anthony Ezell [Synopsys, Inc]
Paper Presentation

From Libraries to Implementation: An IP Analysis and Mixed Vt Methodology
Author(s): Samuel Girgis, Nimit Nguansiri [The MITRE Corp.]
Paper Presentation

MB1 - Assertion Based Verification
Automating Formal Methods to Verify SoC Padring Integration
Author(s): Alan Carlin, Thanh Nguyen [Freescale Semiconductor], Tom Powell [Synopsys, Inc]
Paper Presentation

MB2 - PrimeRail for Power-Sensitive Designs
Predicting Chip-package Resonance of the Power Distribution Network Using PrimeRail (Technical Committee Award Honorable Mention)
Author(s): Gregory Beers, James Kirk, Scott Coates [Agere Systems], Cristian Golovanov, Andrew Cirigliano [Synopsys, Inc]
Paper Presentation

MB3 - JupiterXT
An Evaluation of New Design Size Exploration in JupiterXT
Author(s): Patricia Campbell [ADI], Tlalit Maller [Synopsys, Inc]
Paper Presentation

MC1 - SystemVerilog Do's and Don'ts
Standard Gotchas -- Subtleties in the Verilog and SystemVerilog Standards That Every Engineer Should Know (Technical Committee Award)
Author(s): Stuart Sutherland [Sutherland HDL, Inc], Don Mills [LCDM Engineering]
Paper Presentation

SystemVerilog Event Regions, Race Avoidance & Guidelines
Author(s): Clifford Cummings [Sunburst Designs, Inc], Arturo Salz [Synopsys, Inc]
Paper Presentation

MC4 - Minimizing Test Costs
A Case Study of Hierarchal Scan Compression Implementation (2nd Place - Best Paper)
Author(s): Vincent D'Alessandro, Zahi Abuhamdeh [TranSwitch], David Chagnon, Kristine Westland, Pam Smoot [Synosys, Inc]
Paper Presentation

Fighting Scan Test Time and Data Volumes; Squeezing the Last Drop out of DFT Compiler and TetraMAX
Author(s): Sverre Wichlund [Nordic Semiconductor ASA]
Paper Presentation

TA2 - Optimization Techniques
Search for Context Dependant Optimization Opportunities in Full Chip Netlist
Author(s): Khem Pokhrel [Intel Corp]
Paper Presentation

Technique for Optimizing IBM Power PC 440 Cache SRAM Clock Latency for Highest Performance
Author(s): Paul McGaugh [Broad Reach Engineering], David Castle, Vijay Gullapalli [Synopsys, Inc]
Paper Presentation

TA3 - Innovative Uses of Design Compiler
A Near At-speed Non-pipelined BIST Compiler for Dual Port Embedded Memories using Synopsys Synthesis Flow
Author(s): Arvind Shenoy, Raghavendra KS, Deepak N [Philips Semiconductors]
Paper Presentation

Synthesizing Asynchronous Micropipelines with Design Compiler
Author(s): Alexander Smirnov, Alexander Taubin [Boston University]
Paper Presentation

TA4 - Analog and Mixed Signal Verification
HSIM's Integration within ST Design Flow for Smart Power and High Voltage Technologies (1st Place - Best Paper, Best First-Time Presenter)
Author(s): Branimir Ivetic, Claudio Vignati, Lyes Djama, Stefano Camera [ST Microelectronics], Luong Nguyen [Synopsys, Inc]
Paper Presentation

HSPICE in DDR2 Analysis (Technical Committee Award Honorable Mention)
Author(s): Jim Antonellis [Broadcom Corp]
Paper Presentation

TB1 - RVM/VMM
Complex Register Verification Utilizing RVM Based Register Abstraction Layer (RAL)
Author(s): Brian Slater, Tim Houlihan, Steve Kopac, Jasmin Mulaosmanovic, Venkat Rao, Jeyeth Vijayaraghavan, Sachin Mohan [Cypress Semiconductor]
Paper Presentation

Functional Verification of DVBS2 Receiver ASIC Using RVM
Author(s): Chandrasekar Rajanayagam [ECC Inc./ViaSat Inc.]
Paper Presentation

VMM for Dummies
Author(s): Amre Sultan, Pierre Girodias, Hans van der Schoot [XtremeEDA Corp]
Paper Presentation

Tutorials
MA1
Constraints and Scenario Generation
Author(s):
Tutorial

MB1
Debugging with Discovery Visualization Environment
Author(s):
Tutorial

Verifying RTL Blocks with Assertions
Author(s):
Tutorial

MB2
Dynamic Voltage-drop and EM Analysis for Low Power Designs with PrimeRail
Author(s):
Tutorial

MB3
From Flat to Nearly-Abutted Floorplans with JupiterXT
Author(s):
Tutorial

MB5
Building an Application Interface for PCI Express: A Case Study using AXI
Author(s):
Tutorial

MC2
PrimeTime PX - Methodology for Power Analysis
Author(s):
Tutorial

MC5
DDR2-533 and Beyond with DesignWare Memory Interface IP
Author(s):
Tutorial

TA1
Five Vital Steps to a Robust Testbench with VCS VIP and VMM
Author(s):
Tutorial

Transaction-Level Modeling in a SystemC and SystemVerilog Environment
Author(s):
Tutorial

TA5
Improving Tapeout Predictability with the Pilot Design Environment
Author(s):
Tutorial

TA6
Optimizing for Design - Yield with IC Compiler
Author(s):
Tutorial

TB2
Demystify Variation-aware Design - When You Thought Statistics Was Only for Economics and Theoretical Physics
Author(s):
Tutorial

TB4
Faster Time to Results with Hercules VUE
Author(s):
Tutorial

TB5
S-parameter and Lossy Transmission Line Analysis with HSPICE and CosmosScope
Author(s):
Tutorial

TB6
The IC Compiler GUI: Introduction and Benefits
Author(s):
Tutorial

TC2
Maximizing Post-Layout Simulation Quality. Star-RCXT AMS Extraction
Author(s):
Tutorial

TC3
Design Compiler 2006
Author(s):
Tutorial