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SNUG Boston 2005 Proceedings

User Papers and Presentations
TA1 - Applied Verification Techniques Using Transactors and Dynamic Randomization
Application of Dynamic Random Sequencing in Augmenting Constrained Randomization for System Verification
Author(s): Pei-hsiu Suen, Alicia Strang, Robert Lee [QLogic Corporation]
Paper Presentation

Designing a Reusable Transactor using Transactor Callback Methods - A Case Study
Author(s): John Zook [StarGen Inc] Jason Chen [Synopsys Inc]
Paper Presentation

Method for Data Link Layer and Physical Layer Error Insertion
Author(s): Jim Sweeten [StarGen Inc] Anthony Ezell [Synopsys Inc]
Paper Presentation

TA2 - Low Power Design
Fight the Power - Power Reduction Ideas for ASIC Designers and Tool Providers
Author(s): David Bond, Serag GadelRab, David Reynolds [Tundra Semiconductor]
Paper Presentation

Power Integrity for a Low Power Mixed Signal Consumer Market SoC
Author(s): Badhri Uppiliappan [Analog Devices]
Paper Presentation

Rapid Deployment of an IEM Enabled ARM1176JZFS with Galaxy Power
Author(s): John Biggs, Peter Uttley [ARM Ltd]
Paper Presentation

TA3 - Effective Design And Methodology Techniques
Does HDL Code Quality Matter Anymore? (or Has Design Compiler Made Hardware Engineers Obsolete?)
Author(s): Brian Kane [Cognio Inc]
Paper Presentation

The Living Hell of Identifiers and define_name_rules
Author(s): Maurice Kinney [IBM Microelectronics] Ray Yock, Denise Powell [Synopsys Inc]
Paper Presentation

TA4 - Clock And Power Network Design for Complex SoCs
Analyzing Clock Trees (Best First-Time Presenter, Technical Committee Award Honorable Mention)
Author(s): Jeff Shabel [QUALCOMM Inc]
Paper Presentation

Complex SOC Clocking: Design, Constraints, Strategies and Pitfalls
Author(s): Bart MacLean [Intellon Canada Inc]
Paper Presentation

Power Network Synthesis and Analysis with JupiterXT and PrimePower
Author(s): Thomas Roche, Glen Macon [Analog Devices]
Paper Presentation

TB1 - Application of the Reference Verification Methodology (RVM)
Building Constrained-Random Techniques, Functional Coverage, Scoreboard and the Complete RVM Environment Above the Existing Legacy Verification Environment
Author(s): Virendra Jaiswal, Jitendra Puri [nSys Design Systems Pvt] Fabian Delguste [Synopsys SARL Ltd]
Paper Presentation

Optimizing the Development of a Random-Constrained Self-Checking Verification Environment by Using a Supported Methodology (1st Place - Best Paper, Technical Committee Award Honorable Mention)
Author(s): Nancy Pratt [IBM Systems & Technology Group] Quinn Canfield [Synopsys Inc]
Paper Presentation

Reusable Register Structure for the Reference Verification Methodology
Author(s): Andrew Elms [Tundra Semiconductor Corporation]
Paper Presentation

TB2 - Floorplanning
A Technology Independent Floorplanning Flow Utilizing Design Compiler, JupiterXT and IC Compiler
Author(s): Stefan Creaser, Philip Watson [ARM Ltd] Stephen Edgeworth, Jason Jackson, Antony Newbold [Synopsys UK]
Paper Presentation

Flipchip I/O Floorplanning
Author(s): Jason Werkheiser [Agere Systems], Tom Concannon [Synopsys Inc.]
Paper Presentation

Power Plan Design Techniques for 0.13u Designs
Author(s): Srini Burugu, Sumeer Arya, Steve Doan [Synopsys Inc] Sameer Nayar [PLX Technologies]
Paper Presentation

TB3 - Design Flow And Methodology
AMBA DesignWare® and coreAssembler Simplify the Design Flow and Improve Design Timing for STMicroelectronics Digital Radio Controller & Audio Decoder
Author(s): Sam Bordbar [Synopsys Italia SRL] Mauro Bosco [STMicroelectronics] Andreas Vielhaber [Synopsys GmbH]
Paper Presentation

Applying the Reuse Model to EDA Tool Flows - A DC to Astro Flow using Object-Oriented Perl and XML
Author(s): Kevin Skey [The MITRE Corporation]
Paper Presentation

Managing Scan Test Time using DFT Compiler, TetraMAX, and VTRAN
Author(s): Sverre Wichlund [Nordic Semiconductor ASA]
Paper Presentation

TC1 - Use Of Assertions in Simulation And Formal Verification
Leveraging Assertion Based Verification by using Magellan (Technical Committee Award)
Author(s): Jacob Andersen, Peter Jensen [SyoSil Consulting]
Paper Presentation

Solving Verilog X-Issues by Sequentially Comparing a Design with Itself - You'll never trust unix diff again (3rd Place - Best Paper)
Author(s): Mike Turpin [ARM Ltd]
Paper Presentation

TC2 - System Level Modeling & Physical Design Flow
Doing Your Due Diligence Physically
Author(s): Kenneth Chang [iVivity Inc]
Paper Presentation

Using System Level Modeling to Enhance SoC Verification Lead-Time
Author(s): Remi Francard, Vincent L Homme Desages, Harpreet Singh [STMicroelectronics] Fabian Delguste [Synopsys SARL] Holger Keding [Synopsys GmbH]
Paper Presentation

TC3 - Front-End Design
RDL - Register Description Language
Author(s): Julian Gorfajn [Maxtor Corporation]
Paper Presentation

Using Synthesis in High Performance Microprocessor Design
Author(s): Sunita Adluri [Intel Corporation]
Paper Presentation

TC4 - Verification With SystemVerilog
A Unique Functional Coverage Flow using SystemVerilog and NTB (2nd Place - Best Paper)
Author(s): Richard Raimi [ARM Ltd] Dennis Strouphauer [Synopsys Inc]
Paper Presentation

Object Oriented Testbench Development with VeraHVL and SystemVerilog Assertions (SVA)
Author(s): Glenn Dunlap [Sigmatel]
Paper Presentation

Tutorials
WA2
HSIMplus™ CircuitCheck and Applications
Author(s):
Tutorial

WA3
Galaxy™ Sign-off: Improving Accuracy with PrimeTime® and PrimeTime SI
Author(s):
Tutorial

WA4
Galaxy™ Test: DFT Compiler™, DFT MAX and TetraMAX® 2005.09 Updates
Author(s):
Tutorial

Galaxy™ Test: DFT Compiler™, DFT MAX and TetraMAX® 2005.09 Updates (white background for printing)
Author(s):
Tutorial

WA5
How to Get the Most Productivity Out of VCS 2005.06
Author(s):
Tutorial

WA6
Galaxy Physical: Introduction to IO Planning for IC/Package Co-design
Author(s):
Tutorial

WB3
Galaxy™ Power: Keys to Designing 90-nm ICs for Low-Power Applications
Author(s):
Tutorial

Galaxy™ Power: Keys to Designing 90-nm ICs for Low-Power Applications (white background for printing)
Author(s):
Tutorial

WB5
Advanced SystemVerilog Coverage Metrics with VCS® and Magellan™
Author(s):
Tutorial

WB6
Galaxy™ Synthesis: RTL Coding Guidelines for Datapath Synthesis
Author(s):
Tutorial

WD1
Galaxy™ Synthesis: Design Compiler® 2005 Update
Author(s):
Tutorial

Galaxy™ Synthesis: Design Compiler® 2005 Update (white background for printing)
Author(s):
Tutorial

WD2
DCmatch Analysis in HSPICE
Author(s):
Tutorial

WD3
Methodology to Optimize 90-nm Designs: from RTL to Tapeout with No Fear
Author(s):
Tutorial

WD4
Galaxy™ Physical: Improving Design Yield with Astro™
Author(s):
Tutorial

WD5
Verification as a Mature Discipline: Using the Verification Methodology Manual (VMM) for SystemVerilog to Deliver Measurable, Comprehensive, Productive and Re-usable Verification
Author(s):
Tutorial