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Conference at a Glance

SNUG UK | May 22, 2014

Thursday, May 22, 2014

 Time

Description 

8:15-9:15 Registration and Breakfast
9:15-10:15 Welcome: Mike Bartley, SNUG UK Technical Chair

Program Overview and Logistics: Peter Bell, Senior Technical Manager, SNUG UK

Keynote Address: Designing Change - Leveraging Innovation and Collaboration
Joachim Kunkel, Senior Vice President and General Manager, Solutions Group, Synopsys Inc.
10:15-10:45 Break
 

Track 1

Track 2

Track 3

Track 4

Track 5

Track 6

10:45-12:15

A1 - FPGA Implementation and FPGA-based Prototyping I

Automating SoC RTL to Operational Prototype

A2 - Low Power Implementation I

Power Intent Constraints, how Adoption of IEEE Standards Improves our IP and Design Methodology

Verdi Signoff-LP: Next-Generation Low-Power Static Verification

A3 - High-Performance Implementation I

Emerging Node Design with IC Compiler

Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz

A4 - Verification I

Using Certitude for Relative Functional Qualification of a Re-usable Testbench

Certitude Advanced Tips

A5 - Analog Mixed-Signal Verification I

Low-Power and Simulation Performance in Mixed-Signal

How to Write an Optimum Verilog-A Model
Technical Committee Award - Best Paper Technical Committee Award - Best Paper

A6 - Signoff-Driven Optimisation I

Pimp My Run - Maximising Performance in Signoff STA

PrimeTime Signoff and ECO on a SOC with 70+Million Placeable Cells in 28nm

12:15-13:30 Lunch
13:30-15:00

B1 - FPGA Implementation and FPGA-based Prototyping II

Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS

Putting IP Prototyping on the Fast Track with HAPS Developer eXpress

B2 - Low Power Implementation II

Low-Power Implementation of Complex MIPS Cores

Addressing Challenges Created by the Internet-of-things

B3 - High-Performance Implementation II

IC Compiler II and the Power of 10x: A Product Walk-through

Using IC Compiler II for Design Planning Next Generation Large & Complex Graphics Cores

B4 - Verification II

Vertical Reuse of Block-Level Testbenches - Make it Happen!

A Simplified Approach to Generating Functional Coverage

B5 - Analog Mixed-Signal Verification II

Transistor-Level Static Circuit Analysis, an ERC Solution for Low-Power Custom Digital, Memory, and Analog IP Designs

When Bandgaps Regress: Solving the Challenges of AMS Verification

B6 - Signoff Driven Optimisation II

Reducing Timing ECO Loops using Physically Aware ECO
3rd Place - Best Paper 3rd Place - Best Paper

Static Timing Analysis - Sign-off Timing Margins for Leading-Edge Processes

15:00-15:30 Break
15:30-17:00

C1 - FPGA Implementation and FPGA-based Prototyping III

Efficient Debug and Deployment of FPGA Prototyping Systems

Safety 1st, Infineon implements ProtoLink's FPGA Fault Injection to Provide Safer Roads
Technical Committee - Honorable Mention Technical Committee - Honorable Mention

C2 - Low Power Verification I

The Challenges of Low Power Design: A System-on-Chip with 152 Power Domains

Low-Power Enhancements in the Mixed-Signal Area

C3 - High-Performance Implementation III

Use of Routing Guides in a Highly Congested Design

Adding Interface Transparency to Chip-level Optimisation

C4 - Verification III

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption

Improving Data Monitoring in UVM - Tips and Recommendations

Reverse Gear: Re-imagining Randomization using the VCS Constraint Solver

C5 - Mixed-Signal & Digital Implementation I

Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw

C6 - Design for Test I

Transitioning from DFTMAX to DFTMAX Ultra
2nd Place - Best Paper 2nd Place - Best Place

Scan Insertion and ATPG for C-gate Based Asynchronous Designs
1st Place - Best Paper 1st Place - Best Place

17:00-18:00 Sponsor Expo, Awards and Refreshments