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Conference at a Glance

SNUG Taiwan | September 2-3, 2014

Tuesday, September 02, 2014
Wednesday, September 03, 2014

Tuesday, September 02, 2014

 Time

Description 

8:30-9:10 Registration
9:10-10:00 Welcome and Synopsys Keynote
Addressing Today's Increasing Design Complexity Through Innovation and Collaboration
Dr. Paul Lo, Senior VP, Synopsys Inc.

10:00-10:20 Welcome - SNUG Technical Committee
Dr. Chi-Feng Wu, SNUG Taiwan Technical Committee Chairperson

10:20-10:40 Break
10:40-11:20 Industry Keynote
Industry Opportunities in the OIP Era
Mr. Suk Lee, Senior Director, TSMC
11:20-12:00 Implementation Vision Speech
Dr. Henry Sheng, Group Director, Synopsys
12:00-1:30 Lunch
1:30-3:30

TA1 - Physical Implementation

TA1.1 IC Compiler II and the Power of 10x: A Product Walk-Through

TA1.2 Integrated Tool Flow Certification for N16FinFET Design

TA1.3 Concurrent Clock Tree OCV and Process Corner Variation Reduction
Best Paper AwardBest Paper Award

TA2 - Test

TA2.1 High Scan Compression for Pin-Limited Test by Using DFTMAX Ultra

TA2.2 Strategy of Scan Compression Solution
Honorable Mention Honorable Mention

TA2.3 Low DPPM and Low Cost Testing for All Process Nodes and FinFETs

TA3 - Circuit Simulation

TA3.1 XA-VCS Co-Simulation for Mixed-Signal Design Verification

TA3.2 CustomSim-XA/VCS Co-Simulation in Anpec

TA3.3 TMI Enhancement in Advance Technology Modeling

TA3.4 Memory Characterization by SiliconSmart

TA4 -RTL Verification and Debug

TA4.1 Verification Vision Speech

TA4.2 Missing Piece of Low Power Verification: UPF Code Coverage
Best Paper Award Best paper Award

TA4.3 UVM Verification Using Verification IP

3:30-4:00 Break
4:00-6:00

TB1 - Physical Implementation

TB1.1 Leakage Power Optimization and Congestion Aware Feedthrough Methodology
Best Paper Award Best paper Award

TB1.2 Collaboration on Physical Verification

TB1.3 Emerging Node Design with IC Compiler

TB2 - STA

TB2.1 PrimeTime SIG - Accelerating Design Closure with PrimeTime Advanced Technologies

TB2.2 PrimeTime 2014.06 Highlights

TB3 - Circuit Simulation

TB3.1 System-Level PCB Simulation, Worse-Case Eye and Receiver EQ.

TB3.2 Eliminate DDR3 Timing Errors with HSPICE and SoC/SiP/PCB Co-Design

TB3.3 HSPICE, FineSim, CustomSim Solutions for Tomorrow's Challenge

TB4 - RTL Verification and Debug

TB4.1 Seamless Transition: Test Cases Reuse between PCIe and mPCIe

TB4.2 Building A Robust Memory Controller Verification Environment

TB4.3 Verification Closure Flow

Wednesday, September 03, 2014

 Time

Description 

8:30-9:10 Registration
9:10-10:00 Welcome and Industry Keynote
"IP Driving Innovation: from Pillars to Platforms"
Sir Hossein Yassaie, CEO, Imagination Technologies
10:00-10:20 Break
10:20-10:40 Best Paper Award
Dr. Chi-Feng Wu, SNUG Taiwan Technical Committee Chairperson
10:40-11:20 Industry Keynote
"A Journey to Smart World"
Mr. Denny Liu, Special Assistant, Design Tech, MediaTek Inc.
11:20-12:00 Industry Keynote
"Disruptive Trends - Surfing The Big Wave"
Dr. JJ Wu, Vice President, Strategic Marketing, UMC
12:00-1:30 Lunch
1:30-3:00

WA1 - Physical Implementation

WA1.1 LowPower/High Core Utilization G6200 with TSMC 28nm Process

WA1.2 Low-Power Design Implementation

WA2 - Synthesis

WA2.1 Improving Interactive ECO Efficiency Using Formality Ultra

WA2.2 Design Compiler: What's New and Roadmap

WA3 - System and IP

WA3.1 SoC Design Service with Virtual Platform

WA3.2 Optimizing DDR Memory Efficiency with the DesignWare Enhanced Universal Memory Controller

WA4 - Custom Design Using Laker

WA4.1 Custom Schematic Editing and Simulation Environment of CD-SE

WA4.2 Create Parameterized Device for DAC by Laker UDD

WA4.3 Productive Flow for Analog Design and Layout

WA4.4 Laker TCL Application on Bumping Mask Design

WA5 - VC Apps

WA5.1 An Automated Multi-Rail Macro Extraction Flow by Using VC Apps

WA5.2 Use VC Apps to Analyze Paths Between IP Blocks
Honorable Mention Honorable Mention

WA5.3 Taking Debug Productivity to the Next Level with Your Own VC Apps

3:00-3:30 Break
3:30-5:30

WB1 - Physical Implementation

WB1.1 Latest Advances in PrimeRail In-Design Vector Free Rail Analysis

WB1.2 Rapid Technology Readiness with Plug-in of Lynx Design System

WB1.3 Using Lynx Design System Automation to Accelerate SoC Design Processes — Design QoR Analysis, Custom Design Correlation, IP Validation & Release


WB3 - IP and Ecosystem

WB3.1 SoC Designs in IoT Era - IP Prespective

WB3.2 IP Prototyping Kit

WB3.3 UMC Design Enablements - Advanced Technology IP Solution

WB4 - Custom Design Using Laker

WB4.1 Synopsys Custom Design Solution for TSMC FinFET Technology

WB4.2 iPDK Development and Validation Methodology

WB4.3 Introduction of Galaxy Custom Router

WB4.4 In-Design EM/IR Checking in Laker

WB5 - Emulation and FPGA-Base Prototyping

WB5.1 Multicore System Validation Methodology on ZeBu

WB5.2 Emulation and Simulation Acceleration with ZeBu

WB5.3 Imagination GPU Partition Experience Sharing Using Synopsys HAPS70 and Protocompiler

4:30-7:00 Sponsor Expo/Lucky Draw, Meeting Room B