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Conference at a Glance

SNUG Silicon Valley | March 24-26, 2014

Monday, March 24, 2014
Tuesday, March 25, 2014
Wednesday, March 27, 2014

Monday, March 24, 2014

 Time

Description 

7:30-8:45 Registration and Breakfast
9:00-10:30 Welcome: Jonah Probell, SNUG Technical Chair

Keynote Address: Designing Change
Aart de Geus, Chairman and co-CEO, Synopsys, Inc.
10:30-11:00 Break
 

Implementation 1

Implementation 2

Implementation 3

Circuit Simulation

Verification 1

Verification 2

Characterization & Signoff 1

IP

Prototyping/Systems

11:00-12:30

MA-01 ICC Update

IC Compiler 2013.12 Release Highlights

MA-02 Physical Implementation

Routing DDR PHY Matched Length Signals Using Galaxy Custom Router

MA-03 Low-Power Implementation

Low-Power Implementation of Complex MIPS Cores

Low-Power Design in the FinFET Technology

MA-04 Circuit Simulation

CustomSim-Based Comprehensive EM/IR Analysis, Visualization, and Violation Correction

Low-Power and Simulation Performance in Mixed-Signal

MA-05 Verification Vision

Next Order of Productivity and Performance through Technology and Integration with Verification Compiler

MA-07 Signoff - Physically Aware ECO Flow

An Investigation of the Efficacy of PT-ADV in a Non-Synopsys PnR Flow

PrimeTime ECO - Now Physically Aware

MA-08 DDR4 and LPDDR4 IP

Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM

MA-09 HAPS

Automating SoC RTL to Operational Prototype

12:30-2:00 Networking Lunch
12:15-2:00 MA-10 Implementation Lunch and Learn: Winning the Productivity Challenge - Tapeout Success at the Leading Edge of IC Design
12:30-2:00 MA-11 IP Lunch and Learn: Physical IP Development on FinFET - There's Nothing Planar About It!
2:00-3:30

MB-01 DC Update

Design Compiler 2013.12 Release Highlights

MB-02 Custom Physical Implementation

Best Practices for Custom Layout Productivity: How Laker Users Have Cut Layout Time in Half

MB-03 Physical Implementation

Implementation of Multi-Source Clock Tree Synthesis

Cloning DDR4 RDL Routing With Galaxy Custom Router (GCR) Editing Environment

MB-04 Circuit Simulation

Verification Methodology for Array-Based Memories

Extracting Impulse Responses in HSPICE

MB-05 Verification IP

UVM Verification Using Verification IP

Accelerated Verification of ARM-Based SoCs Using Highly Reconfigurable VIP and Custom Scoreboard

MB-06 Advanced System Verilog Constraints

Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver

Technical Committee Award Winner: 1st Place - Best Paper Technical Committee Award Winner

Interchangeable SystemVerilog Random Constraints

MB-07 Leakage Recovery & ECO

Signoff Leakage Recovery

Utilizing Signoff Based Multi Scenario ECO to Solve Unique Design Challenges

MB-08 Embedded Memories and Logic Libraries

Hardening DSPs for Performance and Power with DesignWare Logic Libraries and Embedded Memories

MB-09 HAPS

Achieving Maximum System Performance on Multi-FPGA designs using HAPS-70 System

High-Speed Reliable Interconnects on HAPS-70 Systems

3:30-3:45 Break
3:45-5:15

MC-01 Advanced Physical Implementation

Innovative Technologies in Physical Implementation for Building Leading Edge SoCs

MC-03 Frontend Implementation

ECO Implementation Assistance and Advanced Debugging Using Formality Ultra

MC-04 Circuit Simulation

Signal Integrity Analysis of High-Speed Serial Links Using HSPICE

Custom WaveView for Advanced Analysis, Debugging and Measurement Automation

MC-05 Verification IP

Advanced Verification Techniques Applied to an ARM AMBA 5 Protocol-Based SoC

MC-06 Verification Methodology & Productivity

The "X" Factor: Address It in RTL Simulations

UVM Transactions: Definitions, Methods, and Usage

Technical Committee Award Winner: 3rd Place - Best Paper Technical Committee Award Winner

MC-07 Advanced Signoff and Design

Synchronization and Metastability

PrimeTime Advanced Waveform Propagation

MC-08 IP

Yes! You Can Use PCI Express for Mobile and Enterprise SoCs

MC-09 Prototyping/Systems

Putting IP and Subsystem Prototyping on the Fast Track

4:00-8:00 Designer Community Expo

Tuesday, March 25, 2014

 Time

Description 

8:00-9:00 Registration and Breakfast
9:00-10:00 Technology Keynote: Innovation - The Thrill and Thorns of Navigating Through Uncharted Territories
Dr. Sebastian Thrun, Founder and CEO of Udacity, VP and Research Fellow at Google, and Professor of Computer Science at Stanford University
10:00-10:30 Break
 

Implementation 1

Implementation 2

Implementation 3

Circuit Simulation

Verification 1

Verification 2

Characterization & Signoff 1

Characterization & Signoff 2

IP

Prototyping/Systems

10:30-12:00

TA-01 Physical Implementation - Data Flow Analysis

Accelerating Floorplan Creation Using DFA in ICC/DE

Using Data Flow Analysis for Floorplanning

TA-02 In-Design Physical Implementation/Verification

Managing Metal Fill and Its Impact on Your Design

In-Design Flows for Faster Tapeouts

TA-03 Test

Low DPPM and Low Cost Testing for All Process Nodes and FinFETs

TA-04 Circuit Simulation

Circuit Simulator Release Update: The Solution for Tomorrow's Challenge

TA-05 UVM Methodology

A Register Layer Gallimaufry

How UVM-1.1d Makes the Case for Unit Testing

TA-06 UVM Methodology

Methodology for Command Line Control of Configurations and Sequences Using Synopsys Discovery I2C VIP

Layering Protocol Verification: A Pragmatic Approach Using UVM

TA-07 Signoff- FinFET & Process Variation Panel

The "Real World" Weighs in on FinFET and Process Variation Impact

TA-09 USB 3.1 IP

Integrating USB 3.1 in Your Next SoC Design

TA-10 Systems

Using Platform Architect MCO to Optimize Your Micro-Server SoC Architecture for Performance and Power

Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO

12:00-1:30 Networking Lunch
12:00-1:30 TA-11 Design Compiler Lunch and Learn: Shrinking Design Area and Schedules for Established and Emerging Nodes
12:00-1:30 TA-12 Verification Lunch and Learn: Addressing the Challenges of SoC Verification
1:30-3:30

TB-01 High-Performance Core Implementation

Performance-Focused Implementation of a Dual-Core ARM Cortex-A57 Processor at the 20nm and 16nm Process Technology Nodes

Speed, Power, and Complexity Exploitation and Exploration for Mobile GPU

AMD Shares Highlights from Their Successful Tapeout of an ARM Cortex-A57 MPCore Processor

TB-02 Low-Power Design

Full-Chip Low-Power Static Verification using Verdi Signoff-LP

Verdi Signoff-LP: Next-Generation Low-Power Static Verification

TB-03 Test

Deploying DFTMAX Ultra: Usability is Paramount

Implementing Hierarchical DFT Architecture for Ultra Large Designs Using DFTMAX Core Wrapping and Test Scheduling

Achieving Extreme Compression for GPU System on Chip Designs

TB-04 Circuit Simulation

Single Executable FineSim Technology for Analog and Full-Chip Simulations, Analyzing Performance, Statistical Variation and Design Violations' Checks

A Framework for Automating Circuit Simulations

TB-05 Simulation Acceleration with ZeBu

Verification of SoC Designs with ZeBu HW Emulator

Deploying ZeBu Transaction-Based Verification on Imagination GPUs

TB-06 Advanced Verification Debug with Verdi

Going Beyond the Waveform: Advanced Debug Techniques in Verdi

TB-07 Library Modeling for STA: POCV Variation and Library Cell Validation

Advanced Node Random Device Variability Modeling and Margining in Characterization and STA

Automating PrimeTime vs. HSPICE Validations

Parametric OCV (POCV): A Viable and Recommended Alternative to AOCV for Variation Aware Static Timing Analysis

Technical Committee Award Winner: 2nd Place - Best Paper Technical Committee Award Winner

TB-08 Custom and Advanced Node Parasitic Extraction

NVIDIA's Advanced Node Custom Design Experience with StarRC

GLOBALFOUNDRIES PDK Development and Tool Qualification

Solving Extraction Challenges at 10nm

TB-09 High Speed PHY IP

Addressing the Challenges of Multi-Protocol High Speed PHY Design

TB-10 Systems

Application of Virtual Prototypes, Current and Future

Using Synopsys VDKs for Developing UEFI and Linux Drivers for Synopsys DesignWare IP Interfaces and ARMv8 Processors

3:30-3:45 Break
3:45-5:15

TC-01 Advanced Physical Implementation

R&D Panel: Get the Inside Track in Physical Implementation

TC-04 Circuit Simulation

Transistor Level Static Circuit Analysis, an ERC Solution for Deep Sub-Micron Low-Power Custom Digital, Memory and Analog IP Designs

TC-05 Verification Coverage Closure

Functional Coverage Database Using UCAPI

Full-Chip Application of an Automated Code Coverage Closure Methodology

TC-06 Power Estimation and Coverage

Early Vector Based Dynamic Power Estimation

Auto Line and Conditional Functional Coverage for DV Code

TC-07 Timing Closure & Characterization for Macros

Differential Clock and Topology Handling in NanoTime

20nm Timing Characterization and Signoff of Advanced FPGA Custom Circuits Using NanoTime

TC-08 Signoff Physical Verification

High-Performance Physical Verification of Advanced Designs at NVIDIA

LVS Ease of Use and Debugging

TC-09 Compound Floating Point Units

Designing Compound Floating Point Units with an Efficient Pre-Validated IP Based Approach

TC-10 Coverity

Introduction to Coverity

4:45-6:30 SNUG Pub

Wednesday, March 26, 2014

Time

Description 

8:00-9:00 Registration and Breakfast
 

Implementation 1

Implementation 2

Verification 1

Verification 2

FPGA

Compute Infrastructure

9:00-10:30

WA-01 Advanced Physical Implemenation

Emerging Node Design with IC Compiler

WA-02 Test

Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System

WA-03 Formal Verification and Functional Qualification

Formal Verification of GPU Level of Detail Datapath Block

Integration of Certitude Coverage Collection

WA-04 Verification Closure

Verification Closure Flow

WA-05 FPGA Synthesis

Effortless Xilinx Vivado IP Flows

WA-06 High Performance Computing for Silicon Design

High-Performance Computing for Silicon Design

10:30-10:45 Break
10:45-12:15

WB-01 Low-Power Implementation

Low-Power Design Implementation

WB-02 Test

Automated Volume Diagnostics for Accelerated Yield Learning in Advanced Nodes

WB-04 Verification Environment Qualification

Certitude Functional Qualification: Applications in the C/C++ Domain

WB-05 VCS Update

VCS 2014.03 Release Highlights

WB-06 FPGA Synthesis

Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goals

WB-07 Compute Farm Resource Selection and Management

CPU Choice, Server Architecture, and BIOS Settings for EDA Tool Performance

Fair Sharing of Compute Resources in a Complex Enterprise Environment

12:15-1:45 Networking Lunch
12:15-1:45

WA-07 Using Lynx Design System Automation to Accelerate Design Processes - SoC Flow, Custom Design Correlation and Regression Throughput

1:45-3:15

WC-01 High Level Synthesis

Using Synphony C Compiler to Speed Implementation of Image Processing IP

WC-02 Implementation

SoC Test, Repair, and Diagnostics with STAR Memory System and STAR Hierarchical System

WC-04 Static Low-Power Verification

Increase Low-Power Verification Productivity

WC-06 FPGA Synthesis

Analyze and Report on Your FPGA Design with Ease Using Tcl

WC-07 Storage and OS Impact on EDA Tools

Accelerating VCS Verification for Faster Time-to-Market (TTM) Through Scalable Parallel Infrastructure

OS Roadmap for EDA Design

3:15-4:00 Awards and Wrap Up
1:45-6:00 WC-08 Verdi Interoperable Apps (VIA) Developers Forum