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Conference at a Glance

SNUG Israel | June 17, 2014

Tuesday, June 17, 2014

 Time

Description 

8:30-9:00 Registration and Breakfast
9:00-9:15 Welcome: Zachi Feldman, Broadcom, SNUG Israel User Chair
9:15-10:45 Synopsys Keynote: Addressing Today's Design Complexity Challenges Through Innovation and Collaboration
Eyal Odiz, Vice President of Engineering, Synopsys, Inc

Industry Keynote: Growing and Addressing New Technology Directions
Shai Cohen, Chief Operating Officer and Co-founder, Mellanox Technologies
10:45-11:15 Break
 

Functional Verification & Prototyping

Implementation 1 & 2

AMS Connectivity IPs ARC & Processor Solutions

11:15-12:40

A1-2 - Functional Verification & Prototyping

Verify! Prototype! Go! A Comprehensive Solution to SoC Verification and Prototyping Challenges

A3 - IC Compiler II

IC Compiler II and the Power of 10x: A Product Walk-Through

A5 - Analog and IP Development on FinFET

Physical IP Development on FinFET - There's Nothing Planar About It!

12:40-13:30 Lunch
 

Functional Verification

Prototyping

Implementation 1

Implementation 2

AMS

Connectivity IPs

ARC & Processor Solutions

ICC - Galaxy Custom Routing Workshop

13:30-15:00

B1 - Emulation and Advanced Verdi Debugging

Verification of SoC Designs with ZeBu HW Emulator

Going Beyond the Waveform: Advanced Debug Techniques in Verdi

B2 - Hybrid Prototyping

Practical Virtual Prototyping - Architecture and Software Development

Balancing Power Performance and User Experience Using Virtual Prototyping

Decreasing T2M by Enabling Early Software design; VDK and HAPS

B3 - Advanced Front-End Design and Updates

Latch Base Design - Alive and Kicking

Faster Design Turnaround Using DC-Explorer for RTL Exploration

Design Compiler 2013.12 Release Highlights

B4 - Low Power Design

Low Power flow (UPF) update

Verdi Signoff-LP: Next-Generation Low-Power Static Verification

Hierarchical Flow With Block Abstraction and Power Domains

B5 - Analog Mixed-Signal Design Experience and Updates

Comprehensive AMS Flow for Submicron SoC Design

Memory Characterization Using SiliconSmart Build-In FineSim-Pro Fast-SpiceTechnology

Low-Power and Simulation Performance in Mixed-Signal

B6 - USB 3.1 and Multi-Protocol High Speed PHY Tutorials

Integrating USB 3.1 in Your Next SoC Design

Addressing the Challenges of Multi-Protocol High Speed SERDES PHY Design

B7 - Application-Specific Processors and DSPs

Application-Specific Processors and DSPs Provide Options to Enhance SOC Designs Performance and Energy Characteristics.

An ARC 770D Based C-Programmable 400Gbps NPU Architected for Layer 2-7 Processing

B8 - ICC-Galaxy Custom Router - Workshop and Prizes!

Hands-on ICC-Galaxy Custom Router Workshop and Prize Draw

15:00-15:20 Break
15:20-16:50

C1 -Verification User Experience

Automate Connectivity Validation Using Verdi's Novas Programmable Interface (NPI)

Effective Flow for Advanced VLSI Process, False-Fails Protected, GL Timing Simulation Flow

Constraint Callbacks

C2 - Fast Prototyping

Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goal

Putting IP and Subsystem Prototyping on the Fast Track

C3 - Solutions For Complex Implementation Challenges

Analyzing Clock Mesh Circuits Using Analog Simulator

Routing DDR PHY Matched Length Signals Using Galaxy Custom Router

Emerging Nodes Design With IC Compiler

C4 - Signoff and ECOs

PrimeTime ECO - Now Physically Aware

ECO Implementation Assistance and Advanced Debugging Using Formality Ultra

Power Dedicated Area Optimization

C5 - Custom Design and Flows for Mixed Analog/Digital Chips

Full Custom Analog IC Design Flow Using Synopsys Tools

Methodologies for Design of Digital Front End in Mixed Signal IC

Circuit Simulator Release Update: The Solution for Tomorrow's Challenge

C6 - DDR4 and MIPI Tutorials

Faster DRAM: What You Need to Know About LPDDR4-3200, DDR4-3200, and Next-Generation DRAM

MIPI In Mobile Applications: Reducing Power with M-PHY, M-PCIe and USB SSIC

C7 - IoT and ARC Processors

High Speed Processing on an Embedded Budget

Ultra-Low Power Processors and Subsystems for IoT

 

16:50-17:00 Best Paper Award and Prize Drawing