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Conference at a Glance

India | June 25 - 26, 2014

Wednesday, June 25, 2014
Thursday, June 26, 2014

Wednesday, June 25, 2014

 Time

Description 

7:30-9:00 Registration and Breakfast
9:00-10:15 Welcome: Arindam Ghosh, Director, Applications Consulting, Global Technical Services, Synopsys

Keynote Address: Designing Change into Semiconductor Techonomics
Aart de Geus, Chairman and co-CEO, Synopsys
10:15-10:30 Break
 

IC Verification

IC Design: Signoff

Custom Design and AMS Verification

IC Design: Test

10:30-12:30

WA1: Synopsys User Sessions

WA1.1 User: A Novel Approach to Estimate Simulation Acceleration Performance Gain in an Emulator

WA1.2 User: Transactor-Based Verification of Baseband SoCs

WA1.3 User: An Alternate Approach to Address Emulation of Complex Clocking Systems in FPGA Platforms
Best Paper Award Winner Award Winner

WA1.4 User: eXtinguishing the 'X' Fire from RTL Testbench and Design to Prevent Gate Level Testbench Bring-Up Heartburns

WB1: Synopsys User and Tutorial Sessions

WB1.1 Tutorial: PrimeTime Best Practices and Feature Updates

WB1.2 User: PrimeTime Based Efficient Approach for CDC and MTBF Checks in a Complex SoC
Best Paper Award Winner Award Winner

WB1.3 User: Next Generation STA Techniques for 140+ Million Gates Multi-Voltage Design

WC1: Synopsys User and Tutorial Sessions

WC1.1 Vision: Mixed-Signal Design Solution - At the Confluence of Analog and Digital

WC1.2 User: A Novel Approach Towards Power Characterization of Compiled Memory IPs

WC1.3 User: Runtime Reduction in High Q Circuits Using Harmonic Balance (HB) Algorithm in HSPICE

WD1: Synopsys User and Tutorial Sessions

WD1.1 Tutorial: Low DPPM and Low Cost Testing for All Process Nodes and FinFETs

WD1.2 User: Serializer Mechanism in Asymmetric Scan Configuration
Best Paper Award Winner Award Winner

WD1.3 User: BIST Area Optimization Using SMS 4.x

WD1.4 User: Power Reduction Methods in Multicore SoC Scan Architecture

12:30-1:30 Lunch
 

IC Verification

IC Design: Signoff

Custom Design and AMS Verification

FPGA

1:30-3:00

WA2: Synopsys User and Tutorial Sessions

WA2.1 Vision: Next Order of Productivity and Performance Through Technology and Integration with Verification Compiler

WB2: Synopsys User Session

WB2.1 User: SMVA-Based Efficient Approach for Timing Closure of a Complex Multi-Voltage DVFS Design

WB2.2 User: Faster Timing Closure in Complex SoCs Using Mode Merging

WB2.3 Tutorial: Addressing ECO Bottlenecks in Parasitic Extraction Using Advanced Flows in StarRC

WC2: Synopsys User Session

WC2.1 User: Solving Challenges in Timing Model Development for Custom Memories Using FineSim

WC2.2 User: DDR4 Functional Verification With XA-VCS

WC2.3 User: Block Level Electromigration for More Effective Reliability Check In Full Custom IPs
Best Paper Award Winner Award Winner

WD2: Synopsys User & Tutorial Session

WD2.1 Tutorial: Putting IP and Subsystem Prototyping on the Fast Track

WD2.2 User: Debugging Complex Run Time Issues Using ProtoLink

3:00-3:15 Break
3:15-5:00

WA3: Synopsys Tutorial Session

WA3.1 Tutorial: Increase Low-Power Verification Productivity

WB3: Synopsys User and Tutorial Session

WB3.1 Tutorial: PrimeTime Advanced Waveform Propagation

WB3.2 User: Ensuring Robust Rail Analysis

WB3.3 User: Design Closure with PrimeTime Physical-Aware ECO Fixing and MPI

WC3: Synopsys User and Tutorial Session

WC3.1 User: A Correct by Construction Layout Placement Flow for Hierarchical Mixed Signal Designs

WC3.2 Tutorial: Transistor Level Static and Dynamic Circuit Analysis, an ERC Solution for Deep Sub-Micron Low-Power Custom Digital, Memory and Analog IP Designs

WD3: User and Tutorial Session

WD3.1 Tutorial: Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goals

WD3.2 User: Composed SoC Validation

WD3.3 User: IP Design - Efficient and Fast Prototyping and Porting to ASIC Using Synopsys Tools
Best Paper Award Winner Award Winner

4:00
5:15-7:30 Designer Community Expo

 

Thursday, June 26, 2014

 Time

Description 

7:30-9:00 Registration and Breakfast
9:00-10:15 Welcome: Arindam Ghosh, Director, Global Technical Services, Synopsys

Keynote Address: System Design Challenges in the Connected World
S. Balajee, Vice President, DS India Labs, Samsung Research Institute Bangalore


10:15-10:30 Break
 

IC Design: Implementation

IC Verification

Systems and IP

IC Design: Low Power

10:30-12:30

TA1: Synopsys User and Tutorial Sessions

TA1.1 Tutorial: IC Compiler II and the Power of 10x: A Product Walk-Through

TA1.2 User: 28nm vs 20nm: A CAD Methodology Perspective

TA1.3 Tutorial: Advanced Custom Routing Using Galaxy Custom Router

TB1: Synopsys User Sessions

TB1.1 User: Interrogating Formal Environment: Uncovering Hidden Details and Weaknesses

TB1.2 User: Unified Verification Flow for Complex Low-Power Designs

TB1.3 User: A Novel Approach to Significant Reduction in Time to First Test Using Configurable SoC Testbenches and VIP Reuse

TB1.4 User: Accelerated Verification of a MIPI CSI2 System Using CSI2 Verification IP

TC1: Synopsys Tutorial Sessions

TC1.1 Tutorial: Physical IP Development on FinFET - There's Nothing Planar About It!

TC1.2 Tutorial: Performance Analysis for the Synopsys DesignWare Universal DDR Memory Controller Using Synopsys Platform Architect MCO

TD1: Synopsys User and Tutorial Sessions

TD1.1 User: Modeling and Implementation of Low-Power Intent for Complex SoC Using UPF2.0

TD1.2 User: Library-Level Low-Power Verification Techniques for ARM Artisan Physical IP

TD1.3 Tutorial: Low-Power Design Implementation

12:30-1:30 Lunch
1:30-3:00

TA2: Synopsys User Session

TA2.1 User: Innovative Techniques to Achieve Optimal QoR with Faster Design Closure Cycle on a Multimillion SoC
Best Paper Award Winner Award Winner

TA2.2 User: Advanced ECO Methodology for ARM Core Subsystem

TA2.3 User: Meeting Clock Requirements for High Frequency Design

TB2: Synopsys Tutorial Session

TB2.1 Tutorial: Taking Debug Productivity to the Next Level with Your Own Verdi Apps

TC2: Synopsys Tutorial & User Session

TC2.1 Tutorial: Integrating USB 3.1 in Your Next SoC Design

TC2.2 User: Mechatronics System Modeling: Saber

TC2.3 User: On the Fly Donut Formation in Compiled HD Memory to Enable Analysis of Biggest Instance

TD2: Synopsys User & Tutorial Session

TD2.1 User: Case Study of Using Verdi Signoff LP for Low Power Checks

TD2.2 User: A Recipe to Implement and Verify Low-Power Architecture

TD2.3 User: Efficient Static and Formal Verification Closure of Low-Power Designs
Best Paper Award Winner Award Winner

3:00-3:15 Break
3:15-5:00

TA3: Synopsys User & Tutorial Sessions

TA3.1 User: A Practical Approach to Achieve Tighter Correlation and QoR From Synthesis Through P&R for a 28nm Design

TA3.2 Tutorial: Emerging Node Design with IC Compiler

TB3: Synopsys Tutorial Session

TB3.1 Tutorial: Verification Closure Flow

TB3.2 Tutorial: Advanced Verification Techniques Applied to ARM AMBA 4 / AMBA 5 Protocol-Based SoCs

TC3: Synopsys User and Tutorial Sessions

TC3.1 Tutorial: Ultra-Low Power Processors and Subsystems for IoT

TC3.2 Tutorial: Best-In-Class Foundation IP for Different Types of Processor Cores

 

5:00-5:30 Best Paper Awards and Lucky Draw