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Conference at a Glance

SNUG Germany | May 27, 2014

Tuesday, May 27, 2014

 Time

Description 

8:00-9:00 Registration and Breakfast
9:00-10:15 Welcome & Introduction: Frank Poppen, OFFIS Research Institute and SNUG Germany Technical Chair

Keynote Address: Designing Change - Leveraging Innovation and Collaboration
Joachim Kunkel, Senior Vice President and General Manager, Solutions Group, Synopsys Inc.
10:15-10:45 Break
 

Track 1

Track 2

Track 3

Track 4

Track 5

Track 6

10:45-12:15

A1 - Implementation - Synthesis & Test/Failure Analysis

Transitioning from DFTMAX to DFTMAX Ultra

ATPG Pattern Generation and Converging the Flow for a Complex Nanometer SoC

Camelot - A CAD-Navigation Tool, Supporting Failure Analysis for Fault Localization

A2 - Implementation - Placement, CTS & Routing

Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs

Use of Concurrent Clock and Data Optimization in Hardening Processor Cores to 1GHz

Applying an IC Compiler Flow to Address the Requirements of Automotive Mixed-Signal Designs
3rd Place - Best Paper

A3 - System Design - Processor Design

Programmability - Enabler for Increased IP Reuse

A4 - Analog Mixed-Signal Verification I

Top-level Verification of HV-CMOS Sensor Chips with FineSim

Top-Level SoC Power-up Simulation Using XA/VCSMX

Analog-on-top AMS Verification - A Practical Approach
Technical Committee - Honorable Mention

A5 - Digital Verification I

Boosting VP and RTL Verification by Leveraging a Reusable UVM Environment

Reverse Gear: Re-Imagining Randomization Using the VCS Constraint Solver

Automotive Microcontroller Peripheral IP Verification: Applying Certitude on SystemC Models
1st Place - Best Paper

A6 - Digital Verification II

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Technical Committee Award - Best Paper

Leveraging SystemVerilog Object-oriented Programming for Distributed Functional Verification

Discrete Real Type Modelling in a Schematic Netlisted Topology

12:15-13:30 Lunch
13:30-15:00

B1 - Implementation - Formal Verification

DC Explorer - Quickstart to Logic Synthesis

ECO Implementation Assistance and Advanced Debugging Using Formality Ultra

B2 - Implementation - Design Planning

Using ICV for Power Network ECO
2nd Place - Best Paper

Using Data Flow Analysis for Floorplanning in IC Compiler and DC Explorer

B3 - System Design - Prototyping & High-Level Synthesis

Hardware Prototyping and Software Debugging of Multi-core Architectures

Implementing Highly Efficient Audio IP Cores Using an HLS Approach

B4 - Analog Mixed-Signal Verification II

Modelling a 0.45µm HV Technology with HiSIM-HV

Experimental Flow for Hard IP Migration Between GLOBALFOUNDRIES 28nm Technologies

Utilizing the Latest System Verilog 2012 Enhancements for Mixed-Signal Verification and High-Performance Real Number Modeling

B5 - Digital Verification III

Reducing Simulation Runtime of RTL Regressions by VCS, Simulation Environment and Test Bench Optimizations

Debugging Embedded Software Using Verdi HW/SW Debug

A Starter's Guide to Using Synopsys Discovery PCIe Verification IP

B6 - UPF Methodology / Advanced STA

Power Intent Constraints: How Adoption of IEEE Standards Improves our IP and Design Methodology

PrimeTime Advanced ECO

15:00-15:30 Break
15:30-17:00

C1 - Implementation - New Technology

IC Compiler II and the Power of 10x: A Product Walk-through

C3 - System Design - IP: Embedded ARC Cores in Automotive

Easing the Road to ISO 26262 Compliance with the ARC EM SEP Processor Core

C4 - Custom Routing

Galaxy Custom Router Workshop

C5 - Verification - New Technology

Verification Vision

17:00-18:30 Awards and Refreshments