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Conference at a Glance

SNUG France | June 10, 2014

Tuesday, June 10, 2014

 Time

Description 

8:30-9:30 Registration and Breakfast
9:30-10:30 Welcome & Introduction: Pierluigi Daglio, STMicroelectronics and SNUG France Technical Chair

Keynote: Designing Change Through Innovation and Collaboration
John Chilton, Senior Vice President and General Manager, Coverity, Synopsys Inc.
10:30-10:45 Break
 

Front-end Implementation

Functional Verification

Physical Design and Signoff

Design for Test and Yield Analysis

Prototyping and Software Testing

AMS Design and Verification

Custom Routing

10:45-12:15

A1 - Early RTL Exploration and Synthesis

Exploration on CPU/GPU Designs with DC Explorer
Technical Committee Award - Honorable Mention SNUG France 2014 - Technical Committee Award - Honorable Mention

Design Compiler 2013.12 Release Highlights

A2 - Testbench Qualification

Qualification of Complex Systems Multi-Purpose Processor Array

Certitude Advanced Tips

Verification Quality Improvement Using Synopsys Certitude C/C++

A3 - Physical Design Implementation

Optimizing Standard Cell Pin Accessibility in 14nmFDSOI with Synopsys Pin Access Checker

Engineering Change Order
3rd Place Best Paper SNUG France 2014 - 3rd Place Best Paper

ICC 2013.12 Release Highlight

A4 - Design for Test and ATPG

Configurable On Chip Clocking Controller Clock Bit Chain Length to Minimize Test Compression OCC Dedicated Scan Access at SOC Level

Generating Pattern to Debug Chain Segments in DFTMAX X-tolerant Mode

DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins

A5 - Accelerate FPGA-based Prototypes

Automating SoC RTL to Operational Prototype

Better, Faster, Sooner: Tips and Tricks to Efficiently Achieve Timing Performance Goal

A6 - Mixed-Signal Verification I

Simulating Voltage Scaling For Real Applications

Advanced CustomSim-VCS Multi Core Usage

Enrich your Mixed-Signal Verification with UPF Simulation

A7 - Galaxy Custom Router

Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw

12:15-13:30 Lunch
13:30-15:00

B1 - Advanced Synthesis and Formal Verification Techniques

Implementation of a Wireless DSP in 40nm Using DC Graphical

Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs

ECO Implementation Assistance Using Formality Ultra

B2 - Adopting UVM Methodology and Next Generation VIPs

Using Synopsys CSI2 VIP for IP-Level Verification

Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption

Debugging System Verilog Testbench with Verdi3

B3 - In-design Physical Closure and Signoff Accuracy

In-Design Automatic DRC Repair Flow Using IC Compiler and IC Validator

Improving STA Productivity at 32nm/28nmFDSOI and Below
1st Place Best Paper SNUG France 2014 - 1st Place Best Paper

PrimeTime ECO - Now Physically Aware

B4 - Improving Test Quality and Yield

Better Faster Stronger Diagnostic Approach with Synopsys' Yield Explorer

Physical Data Loading to Improve Diagnosis Accuracy
2nd Place Best Paper SNUG France 2014 -2nd Place Best Paper

R&D Q&A Session - Volume Diagnostics for Accelerated Yield Learning in Advanced Technology Nodes

B5 - Complex IP and SoC Prototyping

Emulation and Prototyping of Imagination GPUs using ZeBu and HAPS

Putting IP Prototyping on the Fast Track using HAPS Developer eXpress

B6 - Custom Design Methodology and Signal Integrity

Adding a Metal Fringe Capacitance to an iPDK

New Advanced Methodology for Parasitic Extraction Aimed at Post Layout Analysis in BCD Technologies

Signal Integrity Analysis of High-Speed Serial Links Using HSPICE

B7 - Galaxy Custom Router

Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw

15:00-15:30 Break
15:30-17:00

C1 - Low-Power Static Checking

New Generation of Low-power Static Checker

Verdi Signoff-LP: Next-Generation Low-Power Static Verification

C2 - Hardware-based Verification

Accelerating the Validation of a Secure ROM with ZeBu

Verification of SoC Designs with ZeBu HW Emulator

C3 - IC Compiler II

IC Compiler II: A Fast Methodology to a Good Hierarchical Floorplan

New Breakthrough in Physical Design Productivity

IC Compiler II and the Power of 10x: A Product Walk-through

C4 - SMS & SHS Technologies for IEEE 1500 SoC

STAR Hierarchical System (SHS) Architecture Implementation in Full IEEE1500 SoC
Technical Committee Award - 1st Place SNUG France 2014 - Technical Committee Award - 1st Place

Accelerate SoC Testing Using Synopsys' DesignWare STAR Hierarchical System and DesignWare STAR Memory System

C5 - Coverity

Introduction to Coverity

C6 - Mixed-Signal Verification II

Analog-on-top AMS Verification - a Practical Approach

When Bandgaps Regress: Solving the Challenges of AMS Verification

17:00-18:00 Sponsor Expo, Awards and Refreshments