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Conference at a Glance

SNUG UK | May 16, 2013

Thursday, May 16, 2013

 Time

Description 

8:30-9:30 Registration and Breakfast
9:30-10:15 Welcome and Introduction:
Mike Bartley, UK SNUG Technical Chair, TVS Ltd.

Video Message from Aart de Geus, Chairman and Co-CEO, Synopsys, Inc.

Program Overview and Logistics: Peter Bell, Senior Technical Manager, Synopsys UK
10:15-10:45 Break
 

Track 1

Track 2

Track 3

Track 4

Track 5

Track 6

10:45-12:15

A1 - FPGA Implementation & FPGA-based Prototyping I

Effective Implementation of Xilinx 7 Series FPGAs - Methodologies and Techniques for Maximizing Productivity

A2 - Low Power Implementation I

A Power-Centric Timing Optimization Flow for an ARM® Cortex™-A7 Quad Core Processor

A3 - High-Performance Implementation I

Achieving Higher Frequencies for Your Design with Early Clock-gating Optimization and Comprehensive Useful Skew

Introduction of Multi-Bit Banking Solution

A4 - Verification I

VCS Technologies for Best Debug and Analysis

Certitude - Achieving Faster Verification Closure Using Design Mutation Analysis

A5 - Analog Mixed-Signal/Full Custom Design I

A Comparison of Dynamic and Static Approaches for the Creation of Liberty Models for Mixed-Signal Macros

CCS Noise Characterization Solution

A6 - Signoff-Driven Optimisation I

PrimeTime 2012.12 Productivity Features: Mode Merging and Leakage Recovery

Leakage Power Recovery across Multiple Timing Scenarios

12:15-13:30 Networking Lunch
13:30-15:00

B1 - FPGA Implementation & FPGA-based Prototyping II

FPGA Prototyping Visibility with Protolink

Introduction to Transaction-Based Verification and Hybrid Prototyping

B2 - Low Power Implementation II

Power Intent Specification: Successful Integration of Hard Macros

IEEE1801 (UPF2.0): Automated and Flexible Approach to Power Management Insertion

B3 - High-Performance Implementation II

Deploying a Reference Flow for High-Performance GPU Implementation

Achieving Performance Improvements with Design Compiler Block Abstracts

B4 - Verification II

Making the Most of SystemVerilog and UVM: Hints and Tips for New Users

Going from Custom Methodology to UVM? Do it with a Hybrid.

B5 - Analog Mixed-signal/Full Custom Design II

Advanced Process Node Custom Layout

Full Custom Layout Automation with Helix

B6 - Design for Test I

DFT and ATPG for Mixed 2-phase Latch and Edge Triggered Flop-based Designs

A Hybrid ATPG and Application Testing flow to Localize a Complex RF SoC Failure

15:00-15:30 Break
15:30-17:00

C1 - FPGA Implementation & FPGA-based Prototyping III

Complex SOC Prototyping using Xilinx Virtex 7 based HAPS-70 Systems

Bring Up and Debug of FPGA Prototypes

C2 - Low Power Implementation III

Advanced Retention Power Gating: Unlocking Opportunistic Leakage Savings in High-Performance Mobile SoCs

Using Formal Equivalence Verification Tool Efficiently on a UPF Design

C3 - High-Performance Implementation III

Engineering Trade-Offs in the Implementation of a High-Performance ARM® Cortex™-A15 Dual Core Processor

C4 - Low Power Verification

Architecting Power Awareness in a Constrained Random OVM Testbench

Low Power Verification using Power State Table Coverage

C5 - Analog Mixed-signal/Full Custom Design III

Analog and Mixed-signal Verification Methodology Using Verilog-AMS

Circuit Simulator Release Update — Getting Ready for the Next Technology Node

C6 - Design for Test II

Meeting Quality Goals for Gigascale Designs: Trends and Solutions

17:00-18:00 Awards and Refreshments